u-boot.git/drivers/pinctrl/sunxi, branch master

pinctrl: sunxi: a523: change Ethernet pin function name

2025-08-11T23:50:57+00:00

The name of the pin function was changed last minute in the DT, from
emac0 to gmac0.
Adjust the name we use in the pinctrl driver accordingly.

Signed-off-by: Andre Przywara 
Reviewed-by: Jernej Skrabec

pinctrl: sunxi: add Allwinner A523 pinctrl description

2025-07-27T21:57:35+00:00

The new DT pinctrl binding would allow us to read the pinmux values from
the DT, but it is actually easier to just continue with hardcoding the
mux values in the driver, and matching them against the "function" name.

Add the values for the primary and secondary pin controller on the A523.

Signed-off-by: Andre Przywara

pinctrl: sunxi: add Allwinner A100/A133 pinctrl description

2025-03-27T00:26:35+00:00

The Allwinner A100 SoC has been around for a while, and has now seemingly
been replaced with its close sibling A133.

Add the required mapping between the pinmux group strings and their
respective mux value, as far as used by U-Boot proper. Linux has some
basic (clock and pinctrl) support for a while, so we can build on the
names already used there.

Signed-off-by: Andre Przywara 
Acked-by: Jernej Skrabec

pinctrl: sunxi: Avoid using .bss for SPL

2023-11-12T16:46:46+00:00

sunxi platforms put .bss in DRAM, so .bss is not available in SPL before
DRAM controller initialization. Therefore, this buffer must be placed in
the .data section.

Signed-off-by: Samuel Holland 
Reviewed-by: Andre Przywara

sunxi: add Allwinner R528/T113 SoC support

2023-10-22T22:41:52+00:00

This adds the remaining code bits to teach U-Boot about Allwinner's
newest SoC generation. This was introduced with the RISC-V based
Allwinner D1 SoC, which actually shares a die with the ARM cores versions
called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).

This adds the new Kconfig stanza, using the two newly introduced symbols
for the new SoC generation and pincontroller. It also adds the new symbols
to the relavent code places, to set all the hardcoded bits directly.

We need one DT override:
The ARM core version of the DT specifies the CPUX watchdog as
"reserved", which means it won't be recognised by U-Boot. Override this
in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog,
so that the generic reset driver will work.

Signed-off-by: Andre Przywara

pinctrl: sunxi: add Allwinner D1 pinctrl description

2023-10-22T22:41:51+00:00

Apart from using the new pinctrl MMIO register layout, the Allwinner D1
and related SoCs still need to usual set of mux values hardcoded in
U-Boot's pinctrl driver.
Add the values we need so far to this list, so that DM based drivers
will just work without further ado.

Signed-off-by: Andre Przywara

pinctrl: sunxi: remove GPIO_EXTRA_HEADER

2023-10-22T22:40:57+00:00

U-Boot's generic GPIO_EXTRA_HEADER is a convenience symbol to allow code
to more easily include platform specific GPIO headers. This should not
be needed in a DM world anymore, since the generic GPIO framework
handles that nicely.
For Allwinner boards we still need to deal with non-DM GPIO in the SPL,
but this should become the exception, not the rule.

Make this more obvious by removing the definition of GPIO_EXTRA_HEADER,
and just force every legacy user of platform specific GPIO to include
the new sunxi_gpio.h header explicitly. Everyone doing so should feel
ashamed and should find a way to avoid it from now on.

Signed-off-by: Andre Przywara 
Tested-by: Samuel Holland

pinctrl: sunxi: remove struct sunxi_gpio

2023-10-22T22:40:57+00:00

So far every Allwinner SoC used the same basic pincontroller/GPIO
register frame, and just differed by the number of implemented banks and
pins, plus some special functionality from time to time. However the D1
and successors use a slightly different pinctrl register layout.
Use that opportunity to drop "struct sunxi_gpio", that described that
MMIO frame in a C struct. That approach is somewhat frowned upon in the
Linux world and rarely used there, though still popular with U-Boot.

Switching from a C struct to a "base address plus offset" approach allows
to switch between the two models more dynamically, without reverting to
preprocessor macros and #ifdef's.

Model the pinctrl MMIO register frame in the usual "base address +
offset" way, and replace a hard-to-parse CPP macro with a more readable
static function.
All the users get converted over. There are no functional changes at
this point, it just prepares the stages for the D1 and friends.

Signed-off-by: Andre Przywara 
Reviewed-by: Samuel Holland 
Tested-by: Samuel Holland

pinctrl: sunxi: Add NAND pinmuxes

2023-04-28T00:06:57+00:00

NAND is always at function 2 on port C.

Pin lists and mux values were taken from the Linux drivers.

Reviewed-by: Andre Przywara 
Reviewed-by: Jagan Teki 
Signed-off-by: Samuel Holland 
Signed-off-by: Andre Przywara

pinctrl: sunxi: Add P2WI and RSB pinmuxes

2022-12-13T20:33:37+00:00

P2WI and RSB are used to communicate with a PMIC. Most SoCs have only
one possible pinmux. F1C100s has two possibilities, with different mux
values, so omit it until some board needs one of them.

Signed-off-by: Samuel Holland 
Reviewed-by: Andre Przywara 
Signed-off-by: Andre Przywara