Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/u-boot.git/atom/drivers/pinctrl/sunxi?h=v2023.01 2022-12-13T20:33:37Z 2022-12-13T20:33:37Z Samuel Holland samuel@sholland.org 2022-11-18T04:22:27Z urn:sha1:6cad8bea4f6daa9ee268bbf6f88ae35735692cb0 P2WI and RSB are used to communicate with a PMIC. Most SoCs have only one possible pinmux. F1C100s has two possibilities, with different mux values, so omit it until some board needs one of them. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 2022-10-19T13:15:02Z Andre Przywara andre.przywara@arm.com 2022-10-05T22:19:54Z urn:sha1:843ed983a07ee5d8d4e4ac5baa39fc53f12b5f33 Some boards with the Allwinner F1C100s family SoCs use UART1 for its debug UART, so define the pins for the SPL and the pinmux name and mux value for U-Boot proper. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> 2022-04-04T22:24:17Z Samuel Holland samuel@sholland.org 2021-08-28T22:05:35Z urn:sha1:77834dcc5bafb3928d3caa02f676b43487eb36a4 Pin lists and mux values were taken from the Linux drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 2022-04-04T22:24:17Z Samuel Holland samuel@sholland.org 2021-08-28T20:52:52Z urn:sha1:aa4823ce483f1c277775200846c5684697a4669a This is the only possible mux setting for the A64's PWM peripheral. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 2022-04-04T22:24:16Z Samuel Holland samuel@sholland.org 2021-08-28T21:51:03Z urn:sha1:7570c54e46a76a853a1e3f89a7a3e9960e6a511b Pin lists and mux values were taken from the Linux drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 2022-04-04T22:24:16Z Samuel Holland samuel@sholland.org 2021-08-28T20:17:32Z urn:sha1:4c8f11d4afc799f78d8f6a82efcff618bed03f6c Where multiple options were available, the one matching board.c and the device trees was chosen. Pin lists and mux values were taken from the Linux drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> [Andre: fixup H5 I2C1 pinmux] Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 2022-04-04T22:24:16Z Samuel Holland samuel@sholland.org 2021-08-28T18:34:29Z urn:sha1:37b3de432f2ddbcfcebb9bb2ca1d6e783da191f5 Pin lists and mux values were taken from the Linux drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 2022-04-04T22:24:16Z Samuel Holland samuel@sholland.org 2021-08-28T18:13:52Z urn:sha1:7a93644c69f5d856951ae366d4123c44b068716c Pin lists and mux values were taken from the Linux drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 2022-04-04T22:24:16Z Samuel Holland samuel@sholland.org 2021-08-28T18:21:36Z urn:sha1:fcdbbd68d389e9696e707706917b72c21f9f946b Pin lists and mux values were taken from the Linux drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 2022-04-04T22:24:16Z Samuel Holland samuel@sholland.org 2021-08-28T18:00:45Z urn:sha1:470a7bdb61b7eaff62bac70819e7b8190eb48e6a This includes UART0 and R_UART (s_uart) on all supported platforms, plus the additional UART configurations from arch/arm/mach-sunxi/board.c. Pin lists and mux values were taken from the Linux drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>