u-boot.git/drivers/pinctrl, branch v2016.07 Unnamed repository; edit this file 'description' to name the repository. pinctrl: uniphier: add Ethernet pin-mux settings 2016-07-01T20:44:30+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2016-06-29T10:39:01+00:00 fc9da85c6059fa204498c55c61b7dfa2ebf7fff8 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
pinctrl: uniphier: avoid building unneeded pin-mux tables for SPL 2016-07-01T20:44:30+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2016-06-29T10:39:00+00:00 64c1cc4cc5f72f480787bf493a5ebb0696d68bc0 SPL does not use all of the devices, so we can save some memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
SPL does not use all of the devices, so we can save some memory
footprint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
pinctrl: uniphier: support pin configuration for dedicated pins 2016-07-01T20:44:29+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2016-06-29T10:38:59+00:00 5e25b9d5d90205ce9531677e362e9dd9359963b3 PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration (pin biasing, drive strength control), but not pin-muxing. Allow to fill the mux value table with -1 for those pins; pins with mux value -1 will be skipped in the pin-mux set function. The mux value type should be changed from "unsigned" to "int" in order to accommodate -1 as a special case. [ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration
(pin biasing, drive strength control), but not pin-muxing.

Allow to fill the mux value table with -1 for those pins; pins with
mux value -1 will be skipped in the pin-mux set function.  The mux
value type should be changed from "unsigned" to "int" in order to
accommodate -1 as a special case.

[ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ]

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
pinctrl: uniphier: split pinctrl driver for PH1-LD11 and PH1-LD20 2016-07-01T20:44:29+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2016-06-29T10:38:58+00:00 3379987e26956d9eab668a0811a0f0a9a056754f PH1-LD11 and PH1-LD20 have much pin controlling in common, so I added a single driver shared between them in the initial commit. However, the Ethernet pin-mux settings I am going to add are different with each other, and they may diverge more as the progress of development. Split it into two dedicated drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
PH1-LD11 and PH1-LD20 have much pin controlling in common, so I
added a single driver shared between them in the initial commit.

However, the Ethernet pin-mux settings I am going to add are
different with each other, and they may diverge more as the
progress of development.  Split it into two dedicated drivers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
pinctrl: uniphier: allow to have pinctrl node under syscon node 2016-07-01T20:44:29+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2016-06-29T10:38:57+00:00 186c133444152005473955f1feea2e3184740dd6 Currently, the UniPhier pinctrl driver itself is a syscon, but it turned out much more reasonable to make it a child node of a syscon because our syscon node consists of a bunch of system configuration registers, not only pinctrl, but also phy, and misc registers. It is difficult to split the node. This commit allows to migrate to the new DT structure. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
Currently, the UniPhier pinctrl driver itself is a syscon, but it
turned out much more reasonable to make it a child node of a syscon
because our syscon node consists of a bunch of system configuration
registers, not only pinctrl, but also phy, and misc registers.
It is difficult to split the node.  This commit allows to migrate to
the new DT structure.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
pinctrl: uniphier: remove unneeded pin group nand_cs1 2016-06-30T14:49:26+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2016-06-29T10:38:55+00:00 aac641bcf43207feeca5335f5b98d955fe84c257 This SoC does not support NAND CS1. This place-holder is no longer necessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
This SoC does not support NAND CS1.  This place-holder is no longer
necessary.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
pinctrl: uniphier: fix NAND pin-mux setting for PH1-LD11/LD20 2016-06-30T14:49:26+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2016-06-29T10:38:54+00:00 69da34c073ec7cda928e6cc09fe9cb6abdb3eccd My mistake in the initial support patch. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
My mistake in the initial support patch.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
pinctrl: uniphier: remove wrong pin-mux functions for ProXstream2 2016-06-30T14:49:26+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2016-06-29T10:38:53+00:00 4d1065c8d8d9a6b238cbf7151fc11d0bc1e5cd1b These are pin group names, not function names. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
These are pin group names, not function names.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Merge http://git.denx.de/u-boot-samsung 2016-06-06T17:39:43+00:00 Tom Rini trini@konsulko.com 2016-06-06T17:24:23+00:00 d77fa2ff766bbb4b867e791187f78b6033071613 Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/peach-pi_defconfig configs/peach-pit_defconfig 
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	configs/peach-pi_defconfig
	configs/peach-pit_defconfig
rockchip: rk3288: pinctrl: support more pins 2016-05-27T15:00:48+00:00 Sjoerd Simons sjoerd.simons@collabora.co.uk 2016-02-28T21:24:58+00:00 70f7a2cdac6a7f75f27848d689a13ca244b0792b The rgmii_pins node in rk3288.dtsi configures 15 pins. Increase the size of the cell array to accomedate that, otherwise only the first 10 get configured. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org> 
The rgmii_pins node in rk3288.dtsi configures 15 pins. Increase the size
of the cell array to accomedate that, otherwise only the first 10 get
configured.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>