u-boot.git/drivers/pinctrl, branch v2016.11-rc1

pinctrl: add driver for rk3399

2016-09-22T13:32:22Z

This patch add pinctrl driver for rk3399. Signed-off-by: Kever Yang Acked-by: Simon Glass

pinctrl: uniphier: add UniPhier sLD3 pinctrl driver

2016-09-18T14:10:17Z

Add pin-mux support for UniPhier sLD3 SoC. Signed-off-by: Masahiro Yamada

pinctrl: uniphier: support 4bit-width pin-mux register capability

2016-09-18T14:10:11Z

On LD4 SoC or later, the pin-mux registers are 8bit wide, while 4bit wide on sLD3 SoC. Support it for the sLD3 pinctrl driver. Signed-off-by: Masahiro Yamada

pinctrl: uniphier: move register base macros from header to .c file

2016-09-14T13:54:19Z

These macros are only referenced in pinctrl-uniphier-core.c, so they need not reside in a header file. Signed-off-by: Masahiro Yamada

pinctrl: uniphier: add System Bus pin-mux settings

2016-09-14T13:54:19Z

This is needed to get access to UniPhier System Bus (external bus). Signed-off-by: Masahiro Yamada

pinctrl: add driver for meson-gxbb pin controller

2016-09-06T17:18:19Z

Add a pin controller driver for Meson GXBB adapted from Linux kernel. Signed-off-by: Beniamino Galvani Reviewed-by: Simon Glass

pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes

2016-09-06T17:18:19Z

In cases where the pins and groups definitions are in a sub-node, as: uart_a { mux { groups = "uart_tx_a", "uart_rx_a"; function = "uart_a"; }; }; pinctrl_generic_set_state_subnode() returns an error for the top-level node and pinctrl_generic_set_state() fails. Instead, return success so that the child nodes are tried. Signed-off-by: Beniamino Galvani Reviewed-by: Simon Glass Reviewed-by: Masahiro Yamada

pinctrl: fix typos in comment blocks of pinconfig_post_bind()

2016-08-20T18:03:28Z

'-' is never used in function names. Signed-off-by: Masahiro Yamada

pinctrl: at91-pio4: Add pinctrl driver

2016-08-15T20:58:03Z

AT91 PIO4 controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. The pin configuration is performed on specific registers which are shared along with the gpio controller. So regard the pinctrl device as a child of atmel_pio4 device. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass Reviewed-by: Andreas Bießmann

rockchip: rk3288: Fix pinctrl for GPIO bank 0

2016-07-31T13:24:20Z

Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers rather than the GRF registers. In the GRF the top half of the register is used as a mask so that some bits can be updated without affecting the others, but in the PMU this feature is not provided and the top half of the register is reserved. Take the same approach as the Linux driver to update the value via read-modify-write but setting the mask for only the bits that have changed. The PMU registers ignore the top 16 bits so this works for both GRF and PMU iomux registers. Signed-off-by: John Keeping Reviewed-by: Kever Yang