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<title>u-boot.git/drivers/pinctrl, branch v2017.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>pinctrl: imx7ulp: Add new info instance for iomuxc1</title>
<updated>2017-08-23T08:48:15+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2017-08-14T10:09:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7a7bfec39ea8a800c6cce21c3f44544943ea0a8e'/>
<id>7a7bfec39ea8a800c6cce21c3f44544943ea0a8e</id>
<content type='text'>
To i.MX7ULP, we need to create two info instances for
iomux0 and iomux1 respectively, otherwise iomuxc0/1 will
share one info instance and use one base, because imx_pinctrl_probe
will use info to store base address and etc. But iomuxc0/1
actually have different base address.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
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<pre>
To i.MX7ULP, we need to create two info instances for
iomux0 and iomux1 respectively, otherwise iomuxc0/1 will
share one info instance and use one base, because imx_pinctrl_probe
will use info to store base address and etc. But iomuxc0/1
actually have different base address.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: imx: Fix mask when SHARE_MUX_CONF_REG is set</title>
<updated>2017-08-23T08:47:00+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2017-08-14T10:09:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=63fbc59b4f14e6c19b203cca894226874fe68998'/>
<id>63fbc59b4f14e6c19b203cca894226874fe68998</id>
<content type='text'>
when using SHARE_MUX_CONF_REG, wrong mask is used for
writing config value, which causes mux value is cleared.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
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<pre>
when using SHARE_MUX_CONF_REG, wrong mask is used for
writing config value, which causes mux value is cleared.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: uniphier: remove sLD3 SoC support</title>
<updated>2017-08-20T14:05:39+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2017-08-13T00:01:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=00aa453ebf56fc3a2bd5b684467bc912ba59c4d6'/>
<id>00aa453ebf56fc3a2bd5b684467bc912ba59c4d6</id>
<content type='text'>
This SoC is too old.  It is difficult to maintain any longer.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
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<pre>
This SoC is too old.  It is difficult to maintain any longer.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: rk322x: pinctrl: fix IO MASK error on sdcard pin</title>
<updated>2017-08-18T16:00:46+00:00</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2017-08-17T07:17:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=957b4ee3f3114663f120f5003d14e4fa366198fd'/>
<id>957b4ee3f3114663f120f5003d14e4fa366198fd</id>
<content type='text'>
Fix the IOMUX setting for SDcard CMD pin at the same time.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
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<pre>
Fix the IOMUX setting for SDcard CMD pin at the same time.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: rk322x: pinctrl: using compatible name same with dts</title>
<updated>2017-08-18T16:00:29+00:00</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2017-08-17T07:17:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a634236b8d571df7db35ae70bd9a0573fbbec8d2'/>
<id>a634236b8d571df7db35ae70bd9a0573fbbec8d2</id>
<content type='text'>
The dts from kernel is using rk3228-pinctrl as compatible name,
need to sync with it to make the driver work.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
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<pre>
The dts from kernel is using rk3228-pinctrl as compatible name,
need to sync with it to make the driver work.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: pinctrl: rk3368: add SPI support</title>
<updated>2017-08-13T15:12:25+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-07-25T14:25:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e95b6312e52629f9dd7a649e1c8f33e4ce4a664b'/>
<id>e95b6312e52629f9dd7a649e1c8f33e4ce4a664b</id>
<content type='text'>
To implement pinctrl support for the RK3368, we need to add the
bit-definitions to configure the IOMUX and tie these into the
pinctrl framework. This also adds the mapping from the IRQ# back
onto the periheral id for the SPI devices.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
To implement pinctrl support for the RK3368, we need to add the
bit-definitions to configure the IOMUX and tie these into the
pinctrl framework. This also adds the mapping from the IRQ# back
onto the periheral id for the SPI devices.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver</title>
<updated>2017-08-13T15:12:24+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-07-25T15:09:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a49773d6cf2dd81bc4a0e092d0742c3d5d80bed7'/>
<id>a49773d6cf2dd81bc4a0e092d0742c3d5d80bed7</id>
<content type='text'>
There is no real reason to keep the bit-definitions for the IOMUX in
the grf header file (which defines the register layout of the GRF block):
these should only be used by our pinctrl driver (with the possible
exception of early debug-init code in TPL/SPL).

This moves the relevant definitions from the grf_rk3368.h header
into the pinctrl driver pinctrl_rk3368.c.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
There is no real reason to keep the bit-definitions for the IOMUX in
the grf header file (which defines the register layout of the GRF block):
these should only be used by our pinctrl driver (with the possible
exception of early debug-init code in TPL/SPL).

This moves the relevant definitions from the grf_rk3368.h header
into the pinctrl driver pinctrl_rk3368.c.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: pinctrl: rk3368: add support for configuring the MMC pins</title>
<updated>2017-08-13T15:12:23+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-07-14T18:07:11+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=abcde4751e85558f8603dc6d985295c09a491104'/>
<id>abcde4751e85558f8603dc6d985295c09a491104</id>
<content type='text'>
The RK3368 has two SD/MMC controllers that can be used from U-Boot
both during SPL and for booting an OS from the full bootloader stage.
While both are configured to (mostly) sensible settings from the BROM,
additional configuration for the MMC controller is needed to configure
it to 8bit mode.

This adds pinctrl support for the MMC controller.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
The RK3368 has two SD/MMC controllers that can be used from U-Boot
both during SPL and for booting an OS from the full bootloader stage.
While both are configured to (mostly) sensible settings from the BROM,
additional configuration for the MMC controller is needed to configure
it to 8bit mode.

This adds pinctrl support for the MMC controller.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: pinctrl: rk3368: add GMAC (RGMII only) support</title>
<updated>2017-08-13T15:12:23+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-07-14T18:00:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5282a3f162d472e620045434d45189b7d5275e55'/>
<id>5282a3f162d472e620045434d45189b7d5275e55</id>
<content type='text'>
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration.  This commit
adds the pinctrl support for GMAC in RGMII mode:
 * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
 * configures the RGMII pins

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration.  This commit
adds the pinctrl support for GMAC in RGMII mode:
 * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
 * configures the RGMII pins

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: rk3368: grf: use shifted-constants</title>
<updated>2017-08-13T15:12:23+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-07-25T15:01:06+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c1828cf7abaae7283e48bb857283936fdaf2ef72'/>
<id>c1828cf7abaae7283e48bb857283936fdaf2ef72</id>
<content type='text'>
The RK3368 GRF header was still defines with a shifted-mask but with
non-shifted function selectors for the IOMUX defines.  As the RK3368
support is still fresh enough to allow a quick change, we do this now
before having more code use this.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
<content type='xhtml'>
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<pre>
The RK3368 GRF header was still defines with a shifted-mask but with
non-shifted function selectors for the IOMUX defines.  As the RK3368
support is still fresh enough to allow a quick change, we do this now
before having more code use this.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</pre>
</div>
</content>
</entry>
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