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<title>u-boot.git/drivers/pinctrl, branch v2019.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pinctrl?h=v2019.01-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pinctrl?h=v2019.01-rc2'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2018-12-08T00:01:09Z</updated>
<entry>
<title>Merge tag 'u-boot-amlogic-20181207' of git://git.denx.de/u-boot-amlogic</title>
<updated>2018-12-08T00:01:09Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-12-08T00:01:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=10d3e90f46feace58f4141b696d91644e594e3ed'/>
<id>urn:sha1:10d3e90f46feace58f4141b696d91644e594e3ed</id>
<content type='text'>
Two fixes for the Amlogic Pinctrl driver :
- bad usage of clrsetbits_le32
- bad pin definition for AXG Family
</content>
</entry>
<entry>
<title>pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev()</title>
<updated>2018-12-07T13:13:48Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2018-12-03T09:52:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=530b63c2286d8c19b20a15ca57e20af6c0f08739'/>
<id>urn:sha1:530b63c2286d8c19b20a15ca57e20af6c0f08739</id>
<content type='text'>
Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must
be updated.

stm32_pinctrl_get_gpio_dev() returns from a given pin selectors
the corresponding bank gpio device and the gpio_offset inside this
gpio bank.

Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: stm32: Move gpio_dev list filling outside probe()</title>
<updated>2018-12-07T13:13:47Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2018-12-03T09:52:50Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=043550415b09c6ffd2d9c0af28cc977bfae9f166'/>
<id>urn:sha1:043550415b09c6ffd2d9c0af28cc977bfae9f166</id>
<content type='text'>
Move gpio_dev list filling outside probe() to speed-up U-boot
boot sequence execution. This list is populated only when needed.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: meson: axg: Fix GPIO pin offsets</title>
<updated>2018-12-07T10:01:09Z</updated>
<author>
<name>Carlo Caione</name>
<email>ccaione@baylibre.com</email>
</author>
<published>2018-12-06T08:08:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=139ebe9eb9dac96ab72680e7e8ba77ef9b4cc88b'/>
<id>urn:sha1:139ebe9eb9dac96ab72680e7e8ba77ef9b4cc88b</id>
<content type='text'>
The pin number (first and last) in the bank definition is missing the
pin base offset shifting. This is causing a miscalculation when
retrieving the register and pin offsets in the GPIO driver causing the
'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip
(the AO bank is driven correctly because the shifting is already 0).

Signed-off-by: Carlo Caione &lt;ccaione@baylibre.com&gt;
Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: stm32: make pinctrl use hwspinlock</title>
<updated>2018-12-07T04:26:33Z</updated>
<author>
<name>Benjamin Gaignard</name>
<email>benjamin.gaignard@linaro.org</email>
</author>
<published>2018-11-27T12:49:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=075b0185b6e785f08391802dccd3293ce8517a93'/>
<id>urn:sha1:075b0185b6e785f08391802dccd3293ce8517a93</id>
<content type='text'>
Protect configuration registers with a hardware spinlock.

If a hwspinlock is defined in the device-tree node used it
to be sure that none of the others processors on the SoC could
change the configuration at the same time.

Signed-off-by: Benjamin Gaignard &lt;benjamin.gaignard@linaro.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: meson: Fix GPIO direction registers access</title>
<updated>2018-12-05T09:39:17Z</updated>
<author>
<name>Carlo Caione</name>
<email>ccaione@baylibre.com</email>
</author>
<published>2018-12-03T18:00:42Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fb19c7bade45e97112f65671dd0c5855c727675a'/>
<id>urn:sha1:fb19c7bade45e97112f65671dd0c5855c727675a</id>
<content type='text'>
The macros used to set the direction of the GPIO pins are misused,
resulting in a wrong behavior when trying to read the GPIO input level
from U-Boot.

A better macro is also used when setting the output direction.

Signed-off-by: Carlo Caione &lt;ccaione@baylibre.com&gt;
Reviewed-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic</title>
<updated>2018-11-29T20:16:58Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-11-29T14:33:33Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=93e72ac472b537bb4b0c6a97a7e6aab2b37860c6'/>
<id>urn:sha1:93e72ac472b537bb4b0c6a97a7e6aab2b37860c6</id>
<content type='text'>
Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support
</content>
</entry>
<entry>
<title>pinctrl: MediaTek: add pinctrl driver for MT7623 SoC</title>
<updated>2018-11-29T04:04:52Z</updated>
<author>
<name>Ryder Lee</name>
<email>ryder.lee@mediatek.com</email>
</author>
<published>2018-11-15T02:07:59Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=59a8fef34241b041d439cf0de1b9df18b9051259'/>
<id>urn:sha1:59a8fef34241b041d439cf0de1b9df18b9051259</id>
<content type='text'>
This patch adds pinctrl support for MT7623 SoC. And most of the
structures are used to hold the hardware configuration for each
pin.

Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Tested-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: MediaTek: add pinctrl driver for MT7629 SoC</title>
<updated>2018-11-29T04:04:52Z</updated>
<author>
<name>Ryder Lee</name>
<email>ryder.lee@mediatek.com</email>
</author>
<published>2018-11-15T02:07:58Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=01aa9d1d546f9939261fc262f86698ba2fad0bf8'/>
<id>urn:sha1:01aa9d1d546f9939261fc262f86698ba2fad0bf8</id>
<content type='text'>
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range.  Hence the driver also implements the gpio
functionality through UCLASS_GPIO.

This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.

Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: meson: add axg support</title>
<updated>2018-11-26T13:40:52Z</updated>
<author>
<name>Jerome Brunet</name>
<email>jbrunet@baylibre.com</email>
</author>
<published>2018-10-05T07:36:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8587839f19db078e5ba304a6e635e1900efc8e06'/>
<id>urn:sha1:8587839f19db078e5ba304a6e635e1900efc8e06</id>
<content type='text'>
This adds support for the Amlogic AXG SoC pinctrl and GPIO controller
using a specific set of pinctrl functions which differs from the GX SoCs.

Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
</entry>
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