u-boot.git/drivers/pinctrl, branch v2021.01 Unnamed repository; edit this file 'description' to name the repository. pinctrl: meson: fix bit manipulation of pin bias configuration 2020-12-14T18:58:54+00:00 Neil Armstrong narmstrong@baylibre.com 2020-12-14T18:39:07+00:00 5ccd5d2cc98224108ae9fb09593a862c9caa5e80 This fixes the wrong usage of clrsetbits_le32(), badly setting the set argument. Fixes: c4c726c26b ("pinctrl: meson: add pinconf support") Reported-by: Anton Arapov <arapov@gmail.com> Reported-by: Otto Meier <gf435@gmx.net> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> 
This fixes the wrong usage of clrsetbits_le32(), badly setting the set argument.

Fixes: c4c726c26b ("pinctrl: meson: add pinconf support")
Reported-by: Anton Arapov <arapov@gmail.com>
Reported-by: Otto Meier <gf435@gmx.net>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
treewide: Update email address Patrick Delaunay and Patrice Chotard 2020-12-09T09:57:50+00:00 Patrice Chotard patrice.chotard@foss.st.com 2020-12-02T17:47:30+00:00 0f8106f8e0c03839b371eaee1d7459b810d569ec Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> 
Update Patrick and my email address with the one dedicated to
upstream activities.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
pinctrl: stmfx: update pin name 2020-11-25T11:01:53+00:00 Patrick Delaunay patrick.delaunay@st.com 2020-10-28T09:51:57+00:00 e27e96aa804ed6aa44df7cd11b307d981d91f072 Update pin name to avoid duplicated name with SOC GPIO gpio0...gpio15 / agpio0....agpio7: add a stmfx prefix. This pin name can be used in pinmux command. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> 
Update pin name to avoid duplicated name with SOC GPIO
gpio0...gpio15 / agpio0....agpio7: add a stmfx prefix.

This pin name can be used in pinmux command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
pinctrl: stmfx: update pincontrol and gpio device name 2020-11-25T11:01:53+00:00 Patrick Delaunay patrick.delaunay@st.com 2020-10-28T09:51:56+00:00 c2a8181d453ea85829dceb0a523cda71e29ea27a The device name is used in pinmux command and in log trace so it is better to use the parent parent name ("stmfx@42" for example) than a generic name ("pinctrl" or "stmfx-gpio") to identify the device instance. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> 
The device name is used in pinmux command and in log trace
so it is better to use the parent parent name ("stmfx@42" for
example) than a generic name ("pinctrl" or "stmfx-gpio")
to identify the device instance.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
pinctrl: stm32: display bias information for all pins 2020-11-25T11:01:46+00:00 Patrick Delaunay patrick.delaunay@st.com 2020-10-28T09:49:07+00:00 b305dbc08b08ab6681bfae8d33adc4f90fd3b9ad Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> 
Display the bias information for input gpios or AF configuration,
and not only for output pin, as described in Reference manual
(Table 81. Port bit configuration table).

Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
pinctrl: renesas: Drop unused members from struct sh_pfc_pinctrl 2020-11-22T11:49:22+00:00 Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2020-11-04T17:27:04+00:00 46f3282b281ce222bcedd4e158629c5a97882933 Drop unused members from struct sh_pfc_pinctrl. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> 
Drop unused members from struct sh_pfc_pinctrl.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
pinctrl: renesas: r8a7795: Optimize pinctrl image size for R8A774E1 2020-11-22T11:49:22+00:00 Biju Das biju.das.jz@bp.renesas.com 2020-10-28T10:34:25+00:00 2a589b7c51c843e84eb7dbe361c493c2a3551a74 This driver supports both RZ/G2H and R-Car H3 SoCs. Optimize pinctrl image size for RZ/G2H, when support for R-Car H3 (R8A7795) is not enabled Based on the similar patch on Linux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> 
This driver supports both RZ/G2H and R-Car H3 SoCs.
Optimize pinctrl image size for RZ/G2H, when support for R-Car H3
(R8A7795) is not enabled

Based on the similar patch on Linux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A774B1 2020-11-22T11:49:22+00:00 Biju Das biju.das.jz@bp.renesas.com 2020-10-28T10:34:24+00:00 8b00761c062551733addc40024d9cfa3e1b1d839 This driver supports both RZ/G2N and R-Car M3-N SoCs. Optimize pinctrl image size for RZ/G2N, when support for R-Car M3-N (R8A77965) is not enabled. Based on the simialr patch on Linux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> 
This driver supports both RZ/G2N and R-Car M3-N SoCs.
Optimize pinctrl image size for RZ/G2N, when support for R-Car M3-N
(R8A77965) is not enabled.

Based on the simialr patch on Linux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1 2020-11-22T11:49:22+00:00 Biju Das biju.das.jz@bp.renesas.com 2020-10-28T10:34:23+00:00 fee13ae8cb2c4dc8a1582e786efa539077c6ff25 This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs. Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+ (R8A7796[01]) is not enabled. Based on the similar patch on Linux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> 
This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs.
Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+
(R8A7796[01]) is not enabled.

Based on the similar patch on Linux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
pinctrl: renesas: r8a77951: Add R8A774E1 PFC support 2020-11-22T11:49:22+00:00 Biju Das biju.das.jz@bp.renesas.com 2020-10-28T10:34:22+00:00 975154bc2c96c2d349d27f92a014688344d0cbb0 Renesas RZ/G2H (r8a774e1) is pin compatible with R-Car H3 (r8a77951), however it doesn't have several automotive specific peripherals. Add a r8a77951 specific pin groups/functions along with common pin groups/functions for supporting both r8a77951 and r8a774e1 SoC. PFC changes are synced from mainline linux-5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 
Renesas RZ/G2H (r8a774e1) is pin compatible with R-Car H3 (r8a77951),
however it doesn't have several automotive specific peripherals. Add
a r8a77951 specific pin groups/functions along with common pin
groups/functions for supporting both r8a77951 and r8a774e1 SoC.

PFC changes are synced from mainline linux-5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>