u-boot.git/drivers/pinctrl, branch v2021.10 Unnamed repository; edit this file 'description' to name the repository. pinctrl: fix typo 2021-09-14T13:07:18+00:00 Yuan Fang fangyuanseu@gmail.com 2021-09-08T11:06:48+00:00 423e324de2a6ada4e24d97cc7aed1c8a7cd15e5f fix typo in pinctrl Kconfig file to avoid git commit failure on some commit hooks check. Signed-off-by: Yuan Fang <fangyuanseu@gmail.com> 
fix typo in pinctrl Kconfig file to avoid git commit failure on
some commit hooks check.

Signed-off-by: Yuan Fang <fangyuanseu@gmail.com>
pinctrl: Add pinctrl driver for imx8ulp 2021-08-09T12:46:51+00:00 Ye Li ye.li@nxp.com 2021-08-07T08:00:43+00:00 0bf4a77e1f7c2a59cbc9c7d9436d58262760a6d9 Add pinctrl driver for i.MX8ULP Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> 
Add pinctrl driver for i.MX8ULP

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
global: Convert simple_strtoul() with decimal to dectoul() 2021-08-02T17:32:14+00:00 Simon Glass sjg@chromium.org 2021-07-24T15:03:30+00:00 0b1284eb52578e15ec611adc5fee1a9ae68dadea It is a pain to have to specify the value 10 in each call. Add a new dectoul() function and update the code to use it. Signed-off-by: Simon Glass <sjg@chromium.org> 
It is a pain to have to specify the value 10 in each call. Add a new
dectoul() function and update the code to use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
arm64: a37xx: pinctrl: Correct PWM pins definitions 2021-07-31T07:59:58+00:00 Marek Behún marek.behun@nic.cz 2021-07-23T17:57:11+00:00 5534fb4f4833eda4e1a2df1c89a75db72e5e2008 The PWM pins on North Bridge on Armada 37xx can be configured into PWM or GPIO functions. When in PWM function, each pin can also be configured to drive low on 0 and tri-state on 1 (LED mode). The current definitions handle this by declaring two pin groups for each pin: - group "pwmN" with functions "pwm" and "gpio" - group "ledN_od" ("od" for open drain) with functions "led" and "gpio" This is semantically incorrect. The correct definition for each pin should be one group with three functions: "pwm", "led" and "gpio". Change the "pwmN" groups to support "led" function. Remove "ledN_od" groups. This cannot break backwards compatibility with older device trees: no device tree uses it since there is no PWM driver for this SOC yet. Also "ledN_od" groups are not even documented. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> 
The PWM pins on North Bridge on Armada 37xx can be configured into PWM
or GPIO functions. When in PWM function, each pin can also be configured
to drive low on 0 and tri-state on 1 (LED mode).

The current definitions handle this by declaring two pin groups for each
pin:
- group "pwmN" with functions "pwm" and "gpio"
- group "ledN_od" ("od" for open drain) with functions "led" and "gpio"

This is semantically incorrect. The correct definition for each pin
should be one group with three functions: "pwm", "led" and "gpio".

Change the "pwmN" groups to support "led" function.

Remove "ledN_od" groups. This cannot break backwards compatibility with
older device trees: no device tree uses it since there is no PWM driver
for this SOC yet. Also "ledN_od" groups are not even documented.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Rename GPIO_SUPPORT to GPIO 2021-07-28T18:29:36+00:00 Simon Glass sjg@chromium.org 2021-07-11T03:14:30+00:00 83061dbd1c893a9abd1b2566785e100448e3f6a3 Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org> 
Rename these options so that CONFIG_IS_ENABLED can be used with them.

Signed-off-by: Simon Glass <sjg@chromium.org>
pinctrl: Avoid coverity warning when checking width 2021-07-15T22:42:05+00:00 Simon Glass sjg@chromium.org 2021-05-14T01:39:28+00:00 4d159b6f84abeaacb346cfd14a3b0c6fb86f43f9 The width is set up in single_of_to_plat() and can only have three values, all of which result in a non-zero divisor. Add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Coverity (CID: 331154) 
The width is set up in single_of_to_plat() and can only have three values,
all of which result in a non-zero divisor. Add a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 331154)
Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dm 2021-07-07T17:34:42+00:00 Tom Rini trini@konsulko.com 2021-07-07T17:34:42+00:00 7e58a3a148fb94e9ce09fb48d0ddd75c20ee7df9 various minor sandbox improvements 
various minor sandbox improvements
pinctrl: mscc: Fix multiple definition error 2021-07-07T14:17:54+00:00 Tom Rini trini@konsulko.com 2021-05-03T20:48:56+00:00 5503435838f946697e78b9564a45595380a66dff With gcc-11 we get a multiple errors here as the declarations for mscc_pinctrl_ops and mscc_gpio_ops are missing an extern. CC: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Lars Povlsen <lars.povlsen@microchip.com> Cc: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> 
With gcc-11 we get a multiple errors here as the declarations for
mscc_pinctrl_ops and mscc_gpio_ops are missing an extern.

CC: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Lars Povlsen <lars.povlsen@microchip.com>
Cc: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
dm: define LOG_CATEGORY for all uclass 2021-07-06T16:38:03+00:00 Patrick Delaunay patrick.delaunay@foss.st.com 2021-04-27T09:02:19+00:00 b953ec2bca1ebe059366e870eb4bec5e7af9c36b Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
Define LOG_CATEGORY for all uclass to allow filtering with
log command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
pinctrl: renesas: Import R8A779A0 V3U PFC tables 2021-06-24T18:22:17+00:00 Marek Vasut marek.vasut+renesas@gmail.com 2021-04-26T23:55:54+00:00 df8adad57d7dd98163df71598e0963362bed6198 Import R8A779A0 V3U PFC tables from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Add parts of PFC table integration from pinctrl: renesas: Add R8A779A0 V3U PFC tables by Hai Pham <hai.pham.ud@renesas.com>" . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> 
Import R8A779A0 V3U PFC tables from Linux 5.12, commit 9f4ad9e425a1
("Linux 5.12") . Add parts of PFC table integration from
pinctrl: renesas: Add R8A779A0 V3U PFC tables
by Hai Pham <hai.pham.ud@renesas.com>" .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>