u-boot.git/drivers/pinctrl, branch v2023.01 Unnamed repository; edit this file 'description' to name the repository. pinctrl: sunxi: Add P2WI and RSB pinmuxes 2022-12-13T20:33:37+00:00 Samuel Holland samuel@sholland.org 2022-11-18T04:22:27+00:00 6cad8bea4f6daa9ee268bbf6f88ae35735692cb0 P2WI and RSB are used to communicate with a PMIC. Most SoCs have only one possible pinmux. F1C100s has two possibilities, with different mux values, so omit it until some board needs one of them. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
P2WI and RSB are used to communicate with a PMIC. Most SoCs have only
one possible pinmux. F1C100s has two possibilities, with different mux
values, so omit it until some board needs one of them.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Revert "pinctrl: zynqmp: Add support for output-enable and bias-high-impedance" 2022-11-22T14:02:07+00:00 Michal Simek michal.simek@amd.com 2022-10-13T11:05:39+00:00 716527299a496afcbf495d38bd9e5edfd71ce120 This reverts commit 123462e5e534d6e17b1b7d2006734bbe54b03e0a. On systems with older PMUFW using these pinctrl properties can cause system hang because there is missing feature autodetection. When it is implemented support for these two properties should go back. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c2900319ea80484f21692997f296269aee701c1f.1665659138.git.michal.simek@amd.com 
This reverts commit 123462e5e534d6e17b1b7d2006734bbe54b03e0a.

On systems with older PMUFW using these pinctrl properties can cause system
hang because there is missing feature autodetection.
When it is implemented support for these two properties should go back.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c2900319ea80484f21692997f296269aee701c1f.1665659138.git.michal.simek@amd.com
pinctrl: mvebu: Add AlleyCat5 support 2022-11-07T06:46:28+00:00 Chris Packham judge.packham@gmail.com 2022-11-05T04:23:58+00:00 c2499382146664e19b95292888158d9c844f4032 This uses the same IP block as the Armada-8K SoCs. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> 
This uses the same IP block as the Armada-8K SoCs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
pinctrl: nuvoton: Add NPCM8xx pinctrl driver 2022-11-02T17:31:40+00:00 Jim Liu jim.t90615@gmail.com 2022-10-11T08:09:13+00:00 1c1036499f737eeaa2dab4e56d7ff2c3447fce64 Add Nuvoton BMC NPCM845 Pinmux and Pinconf support. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> 
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
suniv: add UART1 support 2022-10-19T13:15:02+00:00 Andre Przywara andre.przywara@arm.com 2022-10-05T22:19:54+00:00 843ed983a07ee5d8d4e4ac5baa39fc53f12b5f33 Some boards with the Allwinner F1C100s family SoCs use UART1 for its debug UART, so define the pins for the SPL and the pinmux name and mux value for U-Boot proper. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> 
Some boards with the Allwinner F1C100s family SoCs use UART1 for its
debug UART, so define the pins for the SPL and the pinmux name and mux
value for U-Boot proper.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
pinctrl: fix buffer size for pinctrl_generic_set_state_prefix() 2022-10-11T19:40:48+00:00 John Keeping john@metanate.com 2022-09-07T11:11:42+00:00 7eda1a95331d1ccd17e5af6fb18bf5577f81a451 This buffer has the concatenated prefix and name written into it, so it must be large enough to cover both strings plus the terminating NUL. Fixes: 92c4a95ec7 ("pinctrl: Add new function pinctrl_generic_set_state_prefix()") Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> 
This buffer has the concatenated prefix and name written into it, so it
must be large enough to cover both strings plus the terminating NUL.

Fixes: 92c4a95ec7 ("pinctrl: Add new function pinctrl_generic_set_state_prefix()")
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
pinctrl: nuvoton: fix set persist error 2022-10-11T19:40:48+00:00 Jim Liu jim.t90615@gmail.com 2022-09-13T06:23:15+00:00 45455e8ff5634e77aede803f9a772dba08b9674f CA9C is cortex A9 watchdog reset control bit. if device set persist mode, it shouldn't set this bit. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> 
CA9C is cortex A9 watchdog reset control bit.
if device set persist mode, it shouldn't set this bit.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
pinctrl: mediatek: add pinctrl driver for MT7986 SoC 2022-09-23T19:09:15+00:00 Weijie Gao weijie.gao@mediatek.com 2022-09-09T11:59:57+00:00 59acdf8afe4a5c676f8b6ed7af48821980a2bda5 This patch adds pinctrl and gpio support for MT7986 SoC Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 
This patch adds pinctrl and gpio support for MT7986 SoC

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
pinctrl: mediatek: add pinctrl driver for MT7981 SoC 2022-09-23T19:09:15+00:00 Weijie Gao weijie.gao@mediatek.com 2022-09-09T11:59:55+00:00 ace67d109719823c05a4c2c7c09b9c71ee82dd9b This patch adds pinctrl and gpio support for MT7981 SoC Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 
This patch adds pinctrl and gpio support for MT7981 SoC

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
pinctrl: at91-pio4: Add support for pinctrl config subnodes 2022-09-19T06:51:04+00:00 Sergiu Moga sergiu.moga@microchip.com 2022-09-01T14:22:42+00:00 7086defa048cc5303291b592192a18d69c6510cf Previously, in order for the `pinctrl-*` DT node properties to be properly processed, the pinctrl's subnodes were limited to only having the `pinmux` property as well as other additional properties (slew-rate, bias-disable, etc.). Now, with this patch the pinctrl driver is made to work similarly to the one from Linux. It can now distinguish between one subnode and a subnode with multiple subnodes. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> 
Previously, in order for the `pinctrl-*` DT node properties
to be properly processed, the pinctrl's subnodes were limited
to only having the `pinmux` property as well as other additional
properties (slew-rate, bias-disable, etc.). Now, with this patch
the pinctrl driver is made to work similarly to the one from Linux.
It can now distinguish between one subnode and a subnode with multiple
subnodes.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>