Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/u-boot.git/atom/drivers/pinctrl?h=v2024.07-rc1 2024-04-04T15:46:45Z 2024-04-04T15:46:45Z Volodymyr Babchuk Volodymyr_Babchuk@epam.com 2024-03-11T21:33:46Z urn:sha1:493f069062b90e7aba3612651a064f2f313cfc68 This patch is the preparation for SM8150 support. This new SoC depending on the particular pin can have different numbers for the same function. For example "rgmii" function for GPIO4 has id=2 while for GPIO59 it has id=1. So, to support this type of SoCs, get_function_mux() callback needs to know for which pin the function is requested. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> 2024-03-11T19:27:20Z Tom Rini trini@konsulko.com 2024-03-11T17:40:06Z urn:sha1:20a0ce574d6642e0dfe651467159039fac48cc4f Prepare v2024.04-rc4 2024-03-04T15:25:41Z Jonas Karlman jonas@kwiboo.se 2024-02-17T12:08:40Z urn:sha1:1d01440b3f14f6648cd672da619489f635cb209c Pinconfig nodes normally bind recursively with PINCTRL_FULL and PINCONF_RECURSIVE enabled. However, during U-Boot proper pre-relocation any node marked with e.g. bootph-all will not bind unless its parent is also marked for pre-reloc. group1 { pinconf1 { bootph-all; }; }; This cause the following warning message to be shown during U-Boot proper pre-reloc stage on Rockchip devices, e.g on RK3568: ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 and on RK3328: ns16550_serial serial@ff130000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 Check pinconfig nodes pre-reloc status recursively to fix this and to make pinconfig_post_bind work same at both U-Boot proper pre-reloc and at TPL/SPL stage. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> 2024-03-02T19:29:36Z Marek Vasut marek.vasut+renesas@mailbox.org 2024-02-27T16:05:55Z urn:sha1:f9aabd457930f5569297f8a0c4449b9768c1e0cf Rename ARCH_RMOBILE to ARCH_RENESAS because all the chips are made by Renesas, while only a subset of them is from the R-Mobile line. Use the following command to perform the rename: " $ git grep -l 'ARCH_RMOBILE' | xargs -I {} sed -i 's@ARCH_RMOBILE@ARCH_RENESAS@g' {} " Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com> 2024-03-02T19:29:36Z Marek Vasut marek.vasut+renesas@mailbox.org 2024-02-27T16:05:46Z urn:sha1:ca40ed6d7f65b15c33f7cbc6b73f13a34fcfe487 Rename rmobile_get_cpu_rev_*() to renesas_get_cpu_rev_*() because all the chips are made by Renesas, while only a subset of them is from the R-Mobile line. Use the following command to perform the rename: " $ git grep -l '\<rmobile_get_cpu_rev_\(integer\|fraction\)\>' | \ xargs -I {} sed -i 's@\<rmobile_get_cpu_rev_\(integer\|fraction\)\>@renesas_get_cpu_rev_\1@g' {} " Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com> 2024-03-01T21:35:52Z Ivan Mikhaylov fr0st61te@gmail.com 2024-01-20T23:28:13Z urn:sha1:88bb4104adab6d92084297c73a685468325d28a9 Add THRU0-3 and SIOPBI/SIOPBO pin groups/functions. Signed-off-by: Ivan Mikhaylov <fr0st61te@gmail.com> 2024-03-01T14:44:37Z Caleb Connolly caleb.connolly@linaro.org 2024-02-26T17:26:21Z urn:sha1:c744e6308951d47f597e5dac450cab5555698246 Use the root compatible strings from upstream Linux, add missing '#clock-cells' property to the gcc node. Adjust some of the msm8916/apq8016 drivers to use the correct upstream compatible properties and DT bindings. This prepares us to switch to upstream DT in a future patch. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> 2024-03-01T14:44:36Z Caleb Connolly caleb.connolly@linaro.org 2024-02-26T17:26:19Z urn:sha1:8048976e9c9943b28aec8b7e4d998e128b39fe70 On the DB410c we support running as a first stage bootloader. This requires initialising the GPIOs which are muxed to UART before they can be used. Add DM_FLAG_PRE_RELOC to the apq8016 pinctrl driver to ensure that we do this early enough. This is required to prevent the first few lines of UART log from being dropped. Reported-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> 2024-03-01T14:44:36Z Caleb Connolly caleb.connolly@linaro.org 2024-02-26T17:26:18Z urn:sha1:97487ac76de85d22653b12c7561e6c007a3b4eb5 Upstream devicetrees label GPIOs with "gpioX", not "GPIO_X", fix this for SoCs where we're now using upstream DT. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> 2024-03-01T14:44:36Z Caleb Connolly caleb.connolly@linaro.org 2024-02-26T17:26:17Z urn:sha1:a245aece2acfbbaf01f41c595f9bfb02a9aedb70 Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>