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<title>u-boot.git/drivers/pwm, branch v2023.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pwm?h=v2023.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pwm?h=v2023.01'/>
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<updated>2022-09-23T19:09:15Z</updated>
<entry>
<title>pwm: mtk: add support for MediaTek MT7981 SoC</title>
<updated>2022-09-23T19:09:15Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2022-09-09T11:59:38Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1ac479587f18f14bbf54242c1ef2769a66d4b634'/>
<id>urn:sha1:1ac479587f18f14bbf54242c1ef2769a66d4b634</id>
<content type='text'>
This patch adds PWM support for MediaTek MT7981 SoC.
MT7981 uses a different register offset so we have to add a version field
to indicate the IP core version.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>pwm: mtk: add support for MediaTek MT7986 SoC</title>
<updated>2022-09-23T19:09:15Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2022-09-09T11:59:36Z</published>
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<id>urn:sha1:c986dd9f5839028e445853e286525c8b19a0e506</id>
<content type='text'>
This patch adds PWM support for MediaTek MT7986 SoC.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>pwm: aspeed: Select SYSCON to get parent detail.</title>
<updated>2022-08-04T17:59:59Z</updated>
<author>
<name>Billy Tsai</name>
<email>billy_tsai@aspeedtech.com</email>
</author>
<published>2022-04-29T03:50:48Z</published>
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<id>urn:sha1:11d30963bc19c400517c4edd83f83ca06775a05c</id>
<content type='text'>
To work correctly, this driver depends on SYSCON to get the base address
from the parent dts node.

Signed-off-by: Billy Tsai &lt;billy_tsai@aspeedtech.com&gt;
Reviewed-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>Rename CONFIG_PWM to CONFIG_PWM_S5P and move to Kconfig</title>
<updated>2022-07-05T21:03:01Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-06-15T16:03:49Z</published>
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<id>urn:sha1:de0a73291550c68a7c7306c2627cbf6484241fef</id>
<content type='text'>
We rename the S5P specific "CONFIG_PWM" to CONFIG_PWM_S5P and move it to
Kconfig.  Given the usage of CONFIG_PWM_NX, we have that select this new
symbol.

Cc: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
</content>
</entry>
<entry>
<title>driver: pwm: pwm-imx: separe dm from non dm implementation</title>
<updated>2022-04-12T17:10:44Z</updated>
<author>
<name>Tommaso Merciai</name>
<email>tommaso.merciai@amarulasolutions.com</email>
</author>
<published>2022-03-26T11:19:08Z</published>
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<id>urn:sha1:d1016610878f2be45edd580867b1980acb0e3745</id>
<content type='text'>
Separe dm implementation from non dm implementation of pwm-imx
driver using CONFIG_DM_PWM

Signed-off-by: Tommaso Merciai &lt;tommaso.merciai@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>drivers: pwm: pwm-imx: move pwm-imx-util into pwm-imx</title>
<updated>2022-04-12T17:10:44Z</updated>
<author>
<name>Tommaso Merciai</name>
<email>tommaso.merciai@amarulasolutions.com</email>
</author>
<published>2022-03-26T11:19:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2c432563dfd0f9976eb9d962bff726ae7b497ae7'/>
<id>urn:sha1:2c432563dfd0f9976eb9d962bff726ae7b497ae7</id>
<content type='text'>
Move pwm_imx_get_parms, pwm_id_to_reg functions into pwm-imx.c
and drop off pwm-imx-util.c

Signed-off-by: Tommaso Merciai &lt;tommaso.merciai@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>driver: pwm: pwm-imx: introduce pwm_dm_imx_get_parms</title>
<updated>2022-04-12T15:33:55Z</updated>
<author>
<name>Tommaso Merciai</name>
<email>tommaso.merciai@amarulasolutions.com</email>
</author>
<published>2022-03-26T11:19:07Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6828b3ecea2ce91eaa9b7636ef50f0439d15464f'/>
<id>urn:sha1:6828b3ecea2ce91eaa9b7636ef50f0439d15464f</id>
<content type='text'>
Introduce pwm_dm_imx_get_parms, dm version of pwm_imx_get_parms.
This function get clock rate using clk dm api

Signed-off-by: Tommaso Merciai &lt;tommaso.merciai@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>driver: pwm: pwm-imx: get and enable per/ipg clock using dm</title>
<updated>2022-04-12T15:33:55Z</updated>
<author>
<name>Tommaso Merciai</name>
<email>tommaso.merciai@amarulasolutions.com</email>
</author>
<published>2022-03-26T11:19:06Z</published>
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<id>urn:sha1:bfc778cb93a33233fa44006ea283b5aa36ad387d</id>
<content type='text'>
Get and enable ipg/per pwms clocks using dm api into imx_pwm_of_to_plat
and imx_pwm_probe driver function

Signed-off-by: Tommaso Merciai &lt;tommaso.merciai@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze</title>
<updated>2022-04-05T15:27:39Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-04-05T15:27:39Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=037ef53cf01c522073a0a930c84c3ca858f032e1'/>
<id>urn:sha1:037ef53cf01c522073a0a930c84c3ca858f032e1</id>
<content type='text'>
Xilinx changes for v2022.07-rc1 v2

xilinx:
- Allow booting bigger kernels till 100MB

zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device

serial_zynq:
- Change fifo behavior in DEBUG mode

zynq_sdhci:
- Fix BASECLK setting calculation

clk_zynqmp:
- Add support for showing video clock

gpio:
- Update slg driver to handle DT flags

net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver

pwm:
- Add driver for cadence PWM

versal:
- Add support for reserved memory

firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations

include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers
</content>
</entry>
<entry>
<title>Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi</title>
<updated>2022-04-05T12:33:32Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-04-05T12:33:32Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4de720e98d552dfda9278516bf788c4a73b3e56f'/>
<id>urn:sha1:4de720e98d552dfda9278516bf788c4a73b3e56f</id>
<content type='text'>
A big part is the DM pinctrl driver, which allows us to get rid of quite
some custom pinmux code and make the whole port much more robust. Many
thanks to Samuel for that nice contribution! There are some more or less
cosmetic warnings about missing clocks right now, I will send the trivial
fixes for that later.
Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0
(secure images) support. Both features are unused at the moment, but I
have an always-secure board that will use that once the DT lands in the
kernel.
On top of those big things we have some smaller fixes, improving the
I2C DM support, fixing some H6/H616 early clock setup and improving the
eMMC boot partition support.

The gitlab CI completed successfully, including the build test for all
161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100
board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
</content>
</entry>
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