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<title>u-boot.git/drivers/ram/Makefile, branch v2021.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ram/Makefile?h=v2021.04</id>
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<updated>2020-10-08T14:58:33Z</updated>
<entry>
<title>ram: move aspeed ram driver into drivers/ directory</title>
<updated>2020-10-08T14:58:33Z</updated>
<author>
<name>Dylan Hung</name>
<email>dylan_hung@aspeedtech.com</email>
</author>
<published>2020-09-07T08:25:06Z</published>
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<id>urn:sha1:5d457f8057962fbd2ae90826fe80b4039f2dba71</id>
<content type='text'>
to improve the maintainability.  It is more easier to modify and add
configurations of the driver in the centralized ram driver directory.

Signed-off-by: Dylan Hung &lt;dylan_hung@aspeedtech.com&gt;
Reviewed-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)</title>
<updated>2020-10-07T18:25:57Z</updated>
<author>
<name>Aaron Williams</name>
<email>awilliams@marvell.com</email>
</author>
<published>2020-09-02T06:29:08Z</published>
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<id>urn:sha1:15afe725f390774af588c21d127b94915b4f1e17</id>
<content type='text'>
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile
integration.

Signed-off-by: Aaron Williams &lt;awilliams@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>sifive: fu540: add ddr driver</title>
<updated>2020-06-04T01:44:08Z</updated>
<author>
<name>Pragnesh Patel</name>
<email>pragnesh.patel@sifive.com</email>
</author>
<published>2020-05-29T06:03:26Z</published>
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<id>urn:sha1:c514a94abf5aa997508ba072b90318ec10655193</id>
<content type='text'>
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)

Signed-off-by: Pragnesh Patel &lt;pragnesh.patel@sifive.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>ram: add SDRAM driver for i.MXRT SoCs</title>
<updated>2020-01-14T21:54:00Z</updated>
<author>
<name>Giulio Benetti</name>
<email>giulio.benetti@benettiengineering.com</email>
</author>
<published>2020-01-10T14:51:44Z</published>
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<id>urn:sha1:cd647fc4fb8e6018089d0e0a3dfa71bd6beffde4</id>
<content type='text'>
Add SDRAM driver for i.MXRT SoCs.

Signed-off-by: Giulio Benetti &lt;giulio.benetti@benettiengineering.com&gt;
</content>
</entry>
<entry>
<title>ram: k3-j721e: Add support for J721E DDR controller</title>
<updated>2019-10-25T21:33:21Z</updated>
<author>
<name>Kevin Scholz</name>
<email>k-scholz@ti.com</email>
</author>
<published>2019-10-07T13:56:36Z</published>
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<id>urn:sha1:3bb3f266ee617384bb282a6818f675b5aca5c371</id>
<content type='text'>
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.

Signed-off-by: Kevin Scholz &lt;k-scholz@ti.com
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</content>
</entry>
<entry>
<title>ram: MediaTek: add DDR3 driver for MT7629 SoC</title>
<updated>2018-11-29T04:04:53Z</updated>
<author>
<name>Ryder Lee</name>
<email>ryder.lee@mediatek.com</email>
</author>
<published>2018-11-15T02:08:03Z</published>
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<id>urn:sha1:60f633efd5fb6018785f8fb624fcac55dba6987e</id>
<content type='text'>
This patch adds a DDR3 driver for MT7629 SoC.

Signed-off-by: Wu Zou &lt;wu.zou@mediatek.com&gt;
Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>ram: Introduce K3 AM654 DDR Sub System driver</title>
<updated>2018-11-16T21:51:58Z</updated>
<author>
<name>Lokesh Vutla</name>
<email>lokeshvutla@ti.com</email>
</author>
<published>2018-11-02T14:21:02Z</published>
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<id>urn:sha1:06bda1259ffc3ef899de70c7fb86b0982a2912f0</id>
<content type='text'>
K3 based AM654 devices has DDR memory subsystem that comprises
Synopys DDR controller, Synopsis DDR phy and wrapper logic to
intergrate these blocks into the device. This DDR subsystem
provides an interface to external SDRAM devices. Adding support
for the initialization of the external SDRAM devices by
configuring the DDRSS registers and using the buitin PHY
routines.

Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Signed-off-by: Andreas Dannenberg &lt;dannenberg@ti.com&gt;
Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
Signed-off-by: Schuyler Patton &lt;spatton@ti.com&gt;
Signed-off-by: James Doublesin &lt;doublesin@ti.com&gt;
</content>
</entry>
<entry>
<title>drivers: cosmetic: Convert SPDX license tags to Linux Kernel style</title>
<updated>2018-10-28T13:26:39Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2018-10-26T07:02:52Z</published>
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<id>urn:sha1:22929e1266e9a61048bfaef381ad4fb2e2fc3ef5</id>
<content type='text'>
Complete in the drivers directory the work started with
commit 83d290c56fab ("SPDX: Convert all of our single
license tags to Linux Kernel style").

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>ram: Add driver for MPC83xx</title>
<updated>2018-09-18T06:01:18Z</updated>
<author>
<name>Mario Six</name>
<email>mario.six@gdsys.cc</email>
</author>
<published>2018-08-06T08:23:30Z</published>
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<id>urn:sha1:e40615565d68465284b3c6a5fc4147f662824a88</id>
<content type='text'>
Add a RAM driver for the MPC83xx architecture.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Mario Six &lt;mario.six@gdsys.cc&gt;
</content>
</entry>
<entry>
<title>ram: stm32mp1: add driver</title>
<updated>2018-03-19T20:14:21Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2018-03-12T09:46:11Z</published>
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<id>urn:sha1:e70f70aa6504bd6387c0a6d117e48383c5048b6b</id>
<content type='text'>
Add driver and binding for stm32mp1 ddr controller and phy

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
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