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<title>u-boot.git/drivers/ram/Makefile, branch v2024.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ram/Makefile?h=v2024.01</id>
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<updated>2023-10-22T22:41:52Z</updated>
<entry>
<title>sunxi: add R528/T113-s3/D1(s) DRAM initialisation code</title>
<updated>2023-10-22T22:41:52Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-12-31T18:38:21Z</published>
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<id>urn:sha1:124289bd56e7598d7846cb3703b4ccaafb5e76cf</id>
<content type='text'>
The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the
same DRAM initialisation code.
Make use of prior art here and lift some code from awboot[1], which
carried init code based on earlier decompilation efforts, but with a
GPL2 license tag.
This code has been heavily reworked and cleaned up, to match previous
DRAM routines for other SoCs, and also to be closer to U-Boot's coding
style and support routines.
The actual DRAM chip timing parameters are included in the main file,
since they cover all DRAM types, and are protected by a new Kconfig
CONFIG_SUNXI_DRAM_TYPE symbol, which allows the compiler to pick only
the relevant settings, at build time.

The relevant DRAM chips/board specific configuration parameters are
delivered via Kconfig, so this code here should work for all supported
SoCs and DRAM chips combinations.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Tested-by: Sam Edwards &lt;CFSworks@gmail.com&gt;
</content>
</entry>
<entry>
<title>board: schneider: add RZN1 board support</title>
<updated>2023-05-13T02:01:30Z</updated>
<author>
<name>Ralph Siemsen</name>
<email>ralph.siemsen@linaro.org</email>
</author>
<published>2023-05-13T01:36:56Z</published>
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<id>urn:sha1:e87c869db3620c9b03b4364e144c19387d7bfd7a</id>
<content type='text'>
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.

The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.

Signed-off-by: Ralph Siemsen &lt;ralph.siemsen@linaro.org&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>ram: cadence: add driver for Cadence EDAC</title>
<updated>2023-05-13T02:01:30Z</updated>
<author>
<name>Ralph Siemsen</name>
<email>ralph.siemsen@linaro.org</email>
</author>
<published>2023-05-13T01:36:53Z</published>
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<id>urn:sha1:2d67a095dcfe249badb077874815fc0a225f9356</id>
<content type='text'>
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.

Signed-off-by: Ralph Siemsen &lt;ralph.siemsen@linaro.org&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>ram: starfive: add ddr driver</title>
<updated>2023-04-20T08:08:44Z</updated>
<author>
<name>Yanhong Wang</name>
<email>yanhong.wang@starfivetech.com</email>
</author>
<published>2023-03-29T03:42:16Z</published>
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<id>urn:sha1:60abbadfc0bb257733bde49658ab86275a269e2b</id>
<content type='text'>
Add driver for StarFive JH7110 to support ddr initialization in SPL.

Signed-off-by: Yanhong Wang &lt;yanhong.wang@starfivetech.com&gt;
Tested-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</content>
</entry>
<entry>
<title>ram: Mark ram-uclass depend on TPL_DM or SPL_DM</title>
<updated>2023-01-16T10:01:10Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:50:47Z</published>
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<id>urn:sha1:78276c531321ef989ae8d9d83144fb0ddd45962f</id>
<content type='text'>
ram-uclass is building irrespective of whether TPL_DM
or SPL_DM is enabled. So control the ram uclass build
based on TPL/SPL_DM.

Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSS</title>
<updated>2021-05-12T11:00:52Z</updated>
<author>
<name>Dave Gerlach</name>
<email>d-gerlach@ti.com</email>
</author>
<published>2021-05-11T15:22:10Z</published>
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<id>urn:sha1:db2438131d75ea0198487296b6c694bded080d11</id>
<content type='text'>
Create a new CONFIG_K3_DDRSS option to select the common parts of the
k3-ddrss driver. Also introduce a choice that depends on the top level
option to select CONFIG_K3_J721E_DDRSS for j721e support, and update
corresponding Kconfig as required.

Signed-off-by: Dave Gerlach &lt;d-gerlach@ti.com&gt;
</content>
</entry>
<entry>
<title>ram: k3-j721e: Rename to k3-ddrss</title>
<updated>2021-05-12T11:00:52Z</updated>
<author>
<name>Dave Gerlach</name>
<email>d-gerlach@ti.com</email>
</author>
<published>2021-05-11T15:22:09Z</published>
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<id>urn:sha1:67124b9a74fca735beefea147bd4177acaa1661a</id>
<content type='text'>
Rename the k3-j721e folder under drivers/ram to k3-ddrss in preparation
of introducing additional support for other platforms to the same
driver.

Signed-off-by: Dave Gerlach &lt;d-gerlach@ti.com&gt;
</content>
</entry>
<entry>
<title>ram: move aspeed ram driver into drivers/ directory</title>
<updated>2020-10-08T14:58:33Z</updated>
<author>
<name>Dylan Hung</name>
<email>dylan_hung@aspeedtech.com</email>
</author>
<published>2020-09-07T08:25:06Z</published>
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<id>urn:sha1:5d457f8057962fbd2ae90826fe80b4039f2dba71</id>
<content type='text'>
to improve the maintainability.  It is more easier to modify and add
configurations of the driver in the centralized ram driver directory.

Signed-off-by: Dylan Hung &lt;dylan_hung@aspeedtech.com&gt;
Reviewed-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)</title>
<updated>2020-10-07T18:25:57Z</updated>
<author>
<name>Aaron Williams</name>
<email>awilliams@marvell.com</email>
</author>
<published>2020-09-02T06:29:08Z</published>
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<id>urn:sha1:15afe725f390774af588c21d127b94915b4f1e17</id>
<content type='text'>
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile
integration.

Signed-off-by: Aaron Williams &lt;awilliams@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>sifive: fu540: add ddr driver</title>
<updated>2020-06-04T01:44:08Z</updated>
<author>
<name>Pragnesh Patel</name>
<email>pragnesh.patel@sifive.com</email>
</author>
<published>2020-05-29T06:03:26Z</published>
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<id>urn:sha1:c514a94abf5aa997508ba072b90318ec10655193</id>
<content type='text'>
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)

Signed-off-by: Pragnesh Patel &lt;pragnesh.patel@sifive.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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