u-boot.git/drivers/ram/Makefile, branch v2025.04

global: Rename SPL_TPL_ to PHASE_

2024-10-11T17:44:48Z

Use PHASE_ as the symbol to select a particular XPL build. This means that SPL_TPL_ is no-longer set. Update the comment in bootstage to refer to this symbol, instead of SPL_ Signed-off-by: Simon Glass

drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11T17:44:48Z

Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass

ram: ast2700: Add DRAM controller initialization

2024-09-11T12:35:03Z

Add driver for AST2700 to initialize DRAM in SPL. This patch also refactors the Kconfig dependency of Aspeed DRAM drivers as some of them are shared among the file structures of RV and ARM ISAs. Signed-off-by: Chia-Wei Wang Acked-by: Leo Yu-Chi Liang

ARM: renesas: Rename ARCH_RMOBILE to ARCH_RENESAS

2024-03-02T19:29:36Z

Rename ARCH_RMOBILE to ARCH_RENESAS because all the chips are made by Renesas, while only a subset of them is from the R-Mobile line. Use the following command to perform the rename: " $ git grep -l 'ARCH_RMOBILE' | xargs -I {} sed -i 's@ARCH_RMOBILE@ARCH_RENESAS@g' {} " Signed-off-by: Marek Vasut Reviewed-by: Paul Barker

sunxi: add R528/T113-s3/D1(s) DRAM initialisation code

2023-10-22T22:41:52Z

The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the same DRAM initialisation code. Make use of prior art here and lift some code from awboot[1], which carried init code based on earlier decompilation efforts, but with a GPL2 license tag. This code has been heavily reworked and cleaned up, to match previous DRAM routines for other SoCs, and also to be closer to U-Boot's coding style and support routines. The actual DRAM chip timing parameters are included in the main file, since they cover all DRAM types, and are protected by a new Kconfig CONFIG_SUNXI_DRAM_TYPE symbol, which allows the compiler to pick only the relevant settings, at build time. The relevant DRAM chips/board specific configuration parameters are delivered via Kconfig, so this code here should work for all supported SoCs and DRAM chips combinations. Signed-off-by: Andre Przywara Tested-by: Sam Edwards

board: schneider: add RZN1 board support

2023-05-13T02:01:30Z

Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which are based on the Reneasas RZ/N1 SoC devices. The intention is to support both boards using a single defconfig, and to handle the differences at runtime. Signed-off-by: Ralph Siemsen Reviewed-by: Marek Vasut

ram: cadence: add driver for Cadence EDAC

2023-05-13T02:01:30Z

Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1. Signed-off-by: Ralph Siemsen Reviewed-by: Marek Vasut

ram: starfive: add ddr driver

2023-04-20T08:08:44Z

Add driver for StarFive JH7110 to support ddr initialization in SPL. Signed-off-by: Yanhong Wang Tested-by: Conor Dooley

ram: Mark ram-uclass depend on TPL_DM or SPL_DM

2023-01-16T10:01:10Z

ram-uclass is building irrespective of whether TPL_DM or SPL_DM is enabled. So control the ram uclass build based on TPL/SPL_DM. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang

ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSS

2021-05-12T11:00:52Z

Create a new CONFIG_K3_DDRSS option to select the common parts of the k3-ddrss driver. Also introduce a choice that depends on the top level option to select CONFIG_K3_J721E_DDRSS for j721e support, and update corresponding Kconfig as required. Signed-off-by: Dave Gerlach