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<title>u-boot.git/drivers/ram/aspeed/Makefile, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ram/aspeed/Makefile?h=master</id>
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<updated>2026-06-29T19:43:21Z</updated>
<entry>
<title>ram: aspeed: add SDRAM controller driver for AST2700</title>
<updated>2026-06-29T19:43:21Z</updated>
<author>
<name>Ryan Chen</name>
<email>ryan_chen@aspeedtech.com</email>
</author>
<published>2026-06-12T09:43:13Z</published>
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<id>urn:sha1:4a72fd9fb09109857303ca64fd259009e1d4b554</id>
<content type='text'>
Add a SDRAM controller driver for the AST2700, derived from the
existing AST2700 controller code used by the Ibex SPL but adapted
to run from ARM U-Boot proper on the Cortex-A35 cores.

The DDR4/DDR5 controller and its DesignWare PHY are programmed by
the Ibex SPL before ARM U-Boot proper takes over. This driver
reads back the configuration left by the SPL, probes the
controller, and exposes ram_info (base and size, with the VGA
carve-out subtracted) via UCLASS_RAM so that dram_init() can
populate gd-&gt;ram_size.

The PHY firmware-load entry points (dwc_ddrphy_phyinit_userCustom_*)
are kept compiled but call a __weak fmc_hdr_get_prebuilt() stub
when ARM U-Boot proper is the caller; the real implementation is
provided by the Ibex SPL via the same fmc_hdr.h descriptor format
(here added for the ARM build).

Adds the supporting register-layout headers under
arch/arm/include/asm/arch-aspeed/:
  - sdram.h:   SDRAM controller and DWC PHY register definitions
  - scu.h:     SCU bits referenced by the SDRAM driver
  - fmc_hdr.h: prebuilt-blob descriptor (binary-compatible with
               arch/riscv/include/asm/arch-ast2700/fmc_hdr.h used
               by the Ibex SPL)

Signed-off-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>ram: ast2700: Add DRAM controller initialization</title>
<updated>2024-09-11T12:35:03Z</updated>
<author>
<name>Chia-Wei Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2024-09-10T09:39:19Z</published>
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<id>urn:sha1:a1ad11ce5249acf4b0f90a096cc975eddb687c23</id>
<content type='text'>
Add driver for AST2700 to initialize DRAM in SPL.

This patch also refactors the Kconfig dependency of
Aspeed DRAM drivers as some of them are shared among
the file structures of RV and ARM ISAs.

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
Acked-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>ram: aspeed: Add AST2600 DRAM control support</title>
<updated>2021-01-18T20:19:15Z</updated>
<author>
<name>Dylan Hung</name>
<email>dylan_hung@aspeedtech.com</email>
</author>
<published>2020-12-14T05:54:24Z</published>
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<id>urn:sha1:fde93143469fbf1ee6fdd3471d72f27dce6ecc5c</id>
<content type='text'>
AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600.
The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb),
512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported.

Signed-off-by: Dylan Hung &lt;dylan_hung@aspeedtech.com&gt;
Signed-off-by: Chia-Wei, Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>ram: move aspeed ram driver into drivers/ directory</title>
<updated>2020-10-08T14:58:33Z</updated>
<author>
<name>Dylan Hung</name>
<email>dylan_hung@aspeedtech.com</email>
</author>
<published>2020-09-07T08:25:06Z</published>
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<id>urn:sha1:5d457f8057962fbd2ae90826fe80b4039f2dba71</id>
<content type='text'>
to improve the maintainability.  It is more easier to modify and add
configurations of the driver in the centralized ram driver directory.

Signed-off-by: Dylan Hung &lt;dylan_hung@aspeedtech.com&gt;
Reviewed-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
</entry>
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