u-boot.git/drivers/ram/aspeed, branch v2024.01

ram: ast2600: Keep MPLL power on

2023-03-06T22:03:56Z

According to the PLL vendor, we should keep the PLL power on, so we shouldn't toggle the power-down bit during PLL initialization. Signed-off-by: Dylan Hung Reviewed-by: Joel Stanley

global: Finish CONFIG -> CFG migration

2023-01-20T17:27:24Z

At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini Reviewed-by: Simon Glass

global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*

2022-12-05T21:06:07Z

The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass

ram: ast2600: Align the RL and WL setting

2022-11-24T21:26:01Z

Use macro to represent the RL and WL setting to ensure the PHY and controller setting are aligned. Review-by: Ryan Chen Signed-off-by: Dylan Hung

ram: ast2600: Improve ddr4 timing and signal quality

2022-11-24T21:25:58Z

Adjust the following settings to get better timing and signal quality. 1. write DQS/DQ delay - 1e6e2304[0] - 1e6e2304[15:8] 2. read DQS/DQ delay - 0x1e6e0298[0] - 0x1e6e0298[15:8] 3. CLK/CA timing - 0x1e6e01a8[31] 4. Read and write termination - change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8]) - change RTT_PARK from disable to 48 ohm (MR5[8:6]) - change RTT_WR from 120 ohm to disable (MR2[11:9]) - change PHY ODT from 40 ohm to 80 ohm (0x1e6e0130[10:8]) Note1: Both DDR-PHY and DDR controller have their own registers for DDR4 Mode Registers (MR0~MR6). This patch introduces macros to synchronize the MR value on both sides. Note2: the waveform meansurement can be found in item #21 of Aspeed AST26x0 Application note (AP note). Review-by: Ryan Chen Signed-off-by: Dylan Hung

ram: ast2600: Fix incorrect statement of the register polling

2022-11-24T21:25:54Z

The condition "~data" in the if-statement is a typo. The original intention is to poll if SDRAM_PHYCTRL0_INIT bit equals to 0. So use "data == 0" for instead. Besides, the bit[1] of "phy_status" register is hardwired to SDRAM_PHYCTRL0_INIT (with inverse logic). Since SDRAM_PHYCTRL0_INIT has already done, remove the unnecessary checking of phy_status[1]. Fixes: fde93143469f ("ram: aspeed: Add AST2600 DRAM control support") Review-by: Ryan Chen Signed-off-by: Dylan Hung

ram: aspeed: Rework kconfig options

2022-03-10T18:49:57Z

Ensure the ASPEED related options are grouped together under the RAM option when enabling support. This also makes some minor grammar corrections and renames options so they present cleanly in menuconfig. There should be no functional change to the configuration or binary. Signed-off-by: Joel Stanley Reviewed-by: Dylan Hung

Kconfig: Remove all default n/no options

2021-08-31T21:47:49Z

default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini

common: Drop asm/global_data.h from common header

2021-02-02T20:33:42Z

Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include at all, so remove that include. Signed-off-by: Simon Glass Signed-off-by: Tom Rini

ram: aspeed: Add AST2600 DRAM control support

2021-01-18T20:19:15Z

AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600. The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb), 512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported. Signed-off-by: Dylan Hung Signed-off-by: Chia-Wei, Wang Reviewed-by: Ryan Chen