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<title>u-boot.git/drivers/ram/k3-ddrss, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>kbuild: Bump the build system to 6.1</title>
<updated>2026-01-02T16:28:14+00:00</updated>
<author>
<name>Sughosh Ganu</name>
<email>sughosh.ganu@linaro.org</email>
</author>
<published>2025-12-16T09:16:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bd3f9ee679b4d1456d0d3c261ab76788950e6096'/>
<id>bd3f9ee679b4d1456d0d3c261ab76788950e6096</id>
<content type='text'>
Our last sync with the kernel was 5.1.

We are so out of sync now, that tracking the patches and backporting
them one by one makes little sense and it's going to take ages.

This is an attempt to sync up Makefiles to 6.1.
Unfortunately due to sheer amount of patches this is not easy to review,
but that's what we decided during a community call for the bump to 5.1,
so we are following the same guidelines here.

Signed-off-by: Sughosh Ganu &lt;sughosh.ganu@linaro.org&gt;
Signed-off-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;a #rebased on -next
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<pre>
Our last sync with the kernel was 5.1.

We are so out of sync now, that tracking the patches and backporting
them one by one makes little sense and it's going to take ages.

This is an attempt to sync up Makefiles to 6.1.
Unfortunately due to sheer amount of patches this is not easy to review,
but that's what we decided during a community call for the bump to 5.1,
so we are following the same guidelines here.

Signed-off-by: Sughosh Ganu &lt;sughosh.ganu@linaro.org&gt;
Signed-off-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;a #rebased on -next
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: k3-ddrss: Support multiple ECC regions for a single controller</title>
<updated>2025-08-19T17:26:20+00:00</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2025-08-12T12:43:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0824703fb2b49ed64edee6f8db483bedfa0189dd'/>
<id>0824703fb2b49ed64edee6f8db483bedfa0189dd</id>
<content type='text'>
K3 Inline ECC mechanism can support up to 3 regions of inline ECC, add
this support for single controller.

Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</content>
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<pre>
K3 Inline ECC mechanism can support up to 3 regions of inline ECC, add
this support for single controller.

Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: k3-ddrss: Add support for partial inline ECC in multi-DDR systems</title>
<updated>2025-08-19T17:26:20+00:00</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2025-08-12T12:43:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d1efbc8d65702f9eb7d032e904e092a2fd3075b3'/>
<id>d1efbc8d65702f9eb7d032e904e092a2fd3075b3</id>
<content type='text'>
The existing approach does not account for interleaving in the DDRs when
setting up regions. There is support for MSMC to calculate the regions
for each DDR, so modify k3_ddrss_probe to set the regions accordingly
for multi-DDR systems.

Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</content>
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<pre>
The existing approach does not account for interleaving in the DDRs when
setting up regions. There is support for MSMC to calculate the regions
for each DDR, so modify k3_ddrss_probe to set the regions accordingly
for multi-DDR systems.

Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: k3-ddrss: Add support for MSMC calculation of DDR inline ECC regions</title>
<updated>2025-08-19T17:26:20+00:00</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2025-08-12T12:43:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c32ac5b3b934942fdcd97ee631ca2362032e0e53'/>
<id>c32ac5b3b934942fdcd97ee631ca2362032e0e53</id>
<content type='text'>
Add support for calculation of the protected regions for each DDR in
multi-DDR systems. Since MSMC is the parent node of the individual DDRs
as well as responsible for their interleaving, it only makes sense for
MSMC to contain the logic for dividing the regions.

Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</content>
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<pre>
Add support for calculation of the protected regions for each DDR in
multi-DDR systems. Since MSMC is the parent node of the individual DDRs
as well as responsible for their interleaving, it only makes sense for
MSMC to contain the logic for dividing the regions.

Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: k3-ddrss: Add support for number of controllers under MSMC</title>
<updated>2025-08-19T17:26:20+00:00</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2025-08-12T12:43:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2310aac8ae0180ad78da1d44657f846610296e4d'/>
<id>2310aac8ae0180ad78da1d44657f846610296e4d</id>
<content type='text'>
In K3 multi-DDR systems, the MSMC is responsible for the interleave
mechanism across all the DDR controllers. Add support for MSMC to obtain
the number of controllers it's responsible for using the DT.

Reviewed-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</content>
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<pre>
In K3 multi-DDR systems, the MSMC is responsible for the interleave
mechanism across all the DDR controllers. Add support for MSMC to obtain
the number of controllers it's responsible for using the DT.

Reviewed-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: k3-ddrss: Add support for a partial inline ECC region</title>
<updated>2025-08-19T17:26:19+00:00</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2025-08-12T12:43:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f43f710122541f870ba164e8121445003032c71c'/>
<id>f43f710122541f870ba164e8121445003032c71c</id>
<content type='text'>
Instead of defaulting to choosing the entire DDR region when enabling
inline ECC, allow picking of a range within the DDR space using DT to
enable.

It expects such a node within the memory node, in the absence of which
we resort to enabling inline ECC for the entire DDR region:

inline_ecc: protected@9e780000 {
        device_type = "ecc";
        reg = &lt;0x9e780000 0x0080000&gt;;
        bootph-all;
};

Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Instead of defaulting to choosing the entire DDR region when enabling
inline ECC, allow picking of a range within the DDR space using DT to
enable.

It expects such a node within the memory node, in the absence of which
we resort to enabling inline ECC for the entire DDR region:

inline_ecc: protected@9e780000 {
        device_type = "ecc";
        reg = &lt;0x9e780000 0x0080000&gt;;
        bootph-all;
};

Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: k3-ddrss: Add comment about ecc_reserved_space</title>
<updated>2025-08-19T17:26:19+00:00</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2025-08-12T12:43:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1c70e33b0aca6d5d84145636400e496feb19c8b9'/>
<id>1c70e33b0aca6d5d84145636400e496feb19c8b9</id>
<content type='text'>
The reserved space needed for storing the parity remains the same no
matter the size of the region that is being protected. Add this as a
comment for better code understanding.

Reviewed-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</content>
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<pre>
The reserved space needed for storing the parity remains the same no
matter the size of the region that is being protected. Add this as a
comment for better code understanding.

Reviewed-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: k3-ddrss: s/K3_DDRSS_MAX_ECC_REGIONS/K3_DDRSS_MAX_ECC_REG</title>
<updated>2025-08-19T17:26:19+00:00</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2025-08-12T12:43:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e511c651f6dd0ec89a4b7dec25140540740cf13e'/>
<id>e511c651f6dd0ec89a4b7dec25140540740cf13e</id>
<content type='text'>
To prevent checkpatch warning once we start using this macro more
frequently, shorten the length of it. While at it, also move the
structure k3_ddrss_ecc_region above k3_msmc so that future patches can
have it as a member of k3_msmc.

Reviewed-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</content>
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<pre>
To prevent checkpatch warning once we start using this macro more
frequently, shorten the length of it. While at it, also move the
structure k3_ddrss_ecc_region above k3_msmc so that future patches can
have it as a member of k3_msmc.

Reviewed-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: k3-ddrss: Use DDR address instead of system address for ecc_regions</title>
<updated>2025-08-19T17:26:19+00:00</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2025-08-12T12:43:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=520d9c2521f4082209ce5121be1b3c1eae98994c'/>
<id>520d9c2521f4082209ce5121be1b3c1eae98994c</id>
<content type='text'>
Let ecc_regions[x].start reflect the start of the ECC region in terms of
DDR addressing rather than system addressing. This will make it easier
to extend the usage of the same ecc_regions structure for multi-DDR
systems as well.

Reviewed-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</content>
<content type='xhtml'>
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<pre>
Let ecc_regions[x].start reflect the start of the ECC region in terms of
DDR addressing rather than system addressing. This will make it easier
to extend the usage of the same ecc_regions structure for multi-DDR
systems as well.

Reviewed-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: k3-ddrss: Use logical and not bitwise</title>
<updated>2025-08-15T20:17:30+00:00</updated>
<author>
<name>Andrew Goodbody</name>
<email>andrew.goodbody@linaro.org</email>
</author>
<published>2025-08-08T10:47:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=460db5b44dba0ec93bbfec3bdf537fba7a487714'/>
<id>460db5b44dba0ec93bbfec3bdf537fba7a487714</id>
<content type='text'>
The test for the interrupt LPDDR4_INTR_BIST_DONE is using a bitwise and
but the test is simple logic so use the more appropriate logical and.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
</content>
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<pre>
The test for the interrupt LPDDR4_INTR_BIST_DONE is using a bitwise and
but the test is simple logic so use the more appropriate logical and.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
</pre>
</div>
</content>
</entry>
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