u-boot.git/drivers/ram/k3-ddrss, branch v2023.04

ram: k3-ddrss: add am62a controller support

2022-12-09T19:10:28Z

TI's am62a family of SoCs uses a new 32bit DDR controller that shares much of the same functionality with the existing am64 and j721e controllers. Select this controller by default when u-boot is build for the am62a Signed-off-by: Bryan Brattlof Reviewed-by: Tom Rini

ram: k3-ddrss: add auto-generated macros for am62a support

2022-12-09T19:10:28Z

The new 32bit DDR controller for TI's am62a family of SoCs shares much of the same functionality with the existing 16bit (am64) and 32bit (j721e) controllers, so this patch reorganizes the existing auto-generated macros for the 16bit and 32bit controllers to make room for the macros for the am62a's controller This patch consists mostly of header/macro renames and additions with a new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new macros during compilation. Signed-off-by: Bryan Brattlof

ram: k3-ddrss: Allow use of dt provided initial frequency

2022-04-20T15:14:39Z

Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR frequency that is set for lpddr4 before initialization of the controller. Make this optional and continue to use PLL bypass frequency as is done currently if ti,ddr-freq0 is not provided. Signed-off-by: Dave Gerlach

ram: k3-ddrss: Fix register name and explain its usage

2022-04-20T15:14:39Z

The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect the maximum possible SDRAM of 2 GB for AM64x (instead of the register's default that says 8 GB, which the AM64x DDR controller wouldn't support). The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG was that of the next register at offset 0x24. Signed-off-by: Dominic Rath

ram: k3-ddrss: Introduce ECC Functionality for full memory space

2022-04-04T23:02:04Z

Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach

ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs

2022-04-04T23:02:04Z

The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by: Dave Gerlach

ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems

2022-02-08T14:41:26Z

In Multi DDR subystems with interleaving support, the following needs to configured, - interleaving granular size and region - EMIFs to be enabled - EMIFs with ecc to be enabled - EMIF separated or interleaved - number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port, by default set to 3 Add support for configuring all the above by using a MSMC device Signed-off-by: Aswath Govindraju

ram: k3-ddrss: Add support for multiple instances of DDR subsystems

2022-02-08T14:41:26Z

The current driver only supports single instance of DRR subsystem. Add support for probing multiple instances of DDR subsystem. Signed-off-by: Aswath Govindraju

ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance

2022-02-08T14:41:26Z

Add a pointer to ddr instance int the lpddr4_privatedata_s structure for supporting mutliple instances of DDR in the drivers. Signed-off-by: Aswath Govindraju

WS cleanup: remove SPACE(s) followed by TAB

2021-09-30T13:08:16Z

Signed-off-by: Wolfgang Denk