u-boot.git/drivers/ram/k3-ddrss, branch v2025.07

ram: k3-ddrss: Set SDRAM_IDX using device private data, ddr_ram_size

2025-01-27T19:26:00Z

The SDRAM_IDX in DDRSS_V2A_CTL_REG describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Set SDRAM_IDX using the device private data, ddr_ram_size for K3 family of SoCs. Signed-off-by: Santhosh Kumar K Reviewed-by: Neha Malcom Francis

ram: k3-ddrss: Remove 'ti,ecc-enable' support

2025-01-14T21:47:07Z

The functionality of enabling Inline ECC is now controlled by CONFIG_K3_INLINE_ECC. So, remove the support for 'ti,ecc-enable' property to avoid redundancy and to ensure the Inline ECC feature is mananged through build-time config. Signed-off-by: Santhosh Kumar K Reviewed-by: Wadim Egorov

ram: k3-ddrss: Enable ECC interrupts

2025-01-14T21:47:07Z

Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts by setting the respective bits in the DDRSS_V2A_INT_SET_REG register. Signed-off-by: Santhosh Kumar K

ram: k3-ddrss: Setup ECC region start and range

2025-01-14T21:47:07Z

Setup the ECC region's start and range using the device private data, ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and range of ECC regions from 32 bits to 64 bits to accommodate for DDR greater than or equal to 4GB. Signed-off-by: Santhosh Kumar K

ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations restricted to 32 bits' issue

2025-01-14T21:47:07Z

As R5 is a 32 bit processor, the RAM banks' base and size calculation is restricted to 32 bits, which results in wrong values if bank's base is greater than 32 bits or bank's size is greater than or equal to 4GB. So, add k3_ddrss_ddr_bank_base_size_calc() to get the base address and size of RAM's banks from the device tree memory node, and store in a 64 bit device private data which can be used for ECC reserved memory calculation, Setting ECC range and Fixing up bank size in device tree when ECC is enabled. Signed-off-by: Santhosh Kumar K Reviewed-by: Wadim Egorov

ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming

2025-01-14T21:47:07Z

The 1-bit inline ECC support in TI's DDRSS bridge requires the configured memory regions to be preloaded with a pattern before use. This is done by the k3-ddrss driver from the R5 SPL in a 'for' loop. It takes around 10 seconds to fill 2GB of memory, for example. Memset can cut the time in half and using DMA currently yields a similar result. The BIST engine of DDR controller provides support for initializing any memory region with a pattern. This bypasses the DDRSS bridge, so the required inline ECC data is not computed and populated in the memory. For some values like zero, the computed ECC syndrome is also zero and we can use these values to preload the memory from the DDR controller, without the assistance of the bridge. The registers involved in the process are described in the 'DDR controller registers' topic in [1] AM62 and [2] J721E reference manuals. The patch replaces the 'for' loop memory fill function with the BIST memory initialization procedure. This cuts the time to preload the 2GB memory from 10 seconds down to 1 second. The bist preload function uses the lpddr4 APIs in the k3-ddrss, so this is compatible with devices with both 16-bit LPDDR4 and 32-bit LPDDR4 interfaces (e.g J721E). [1] AM62x: https://www.ti.com/lit/pdf/spruiv7 [2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1 Signed-off-by: Georgi Vlaev Signed-off-by: Santhosh Kumar K

ram: k3-ddrss: drop debug() in timing-sensitive sequence

2024-12-06T22:37:39Z

Those debug() calls might be useful, but beware. They can cause the DDR controller to hang if we do not run the sequence quickly enough. They usually are not an issue with upstream U-Boot and the default DDR config, but they have become troublesome with custom DDR configs. Drop those debug() statements that shouldn't be present in time-sensitive code, to avoid anyone else falling into the trap. Signed-off-by: Théo Lebrun

ram: k3-ddrss: Handle error properly in lpddr4_start

2024-09-24T14:17:54Z

In lpddr4_start function error returned by lpddr4_enablepiinitiator may go undetected due to overwrite of return code. Add support to handle error in above case. Reported-by: Andreas Dannenberg Signed-off-by: Udit Kumar Reviewed-by: Bryan Brattlof

Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"

2024-05-20T19:35:03Z

As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

2024-05-19T14:16:36Z

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman Signed-off-by: Tom Rini