u-boot.git/drivers/ram/renesas, branch master

ram: renesas: dbsc5: Add Renesas R-Car Gen5 DBSC5 driver

2026-06-16T03:38:25Z

Add Renesas R-Car Gen5 DBSC5 DRAM controller driver. This driver is currently capable of bringing LPDDR5X DRAM on Renesas R-Car X5H Ironhide board. Further boards can be supported by supplying board specific DRAM configuration data via dbsc5_get_board_data(). The driver reuses parts of previous DBSC5 driver, but due to hardware changes, can not be fully integrated into existing DBSC and DRAM driver, therefore the currentl DBSC and DRAM drivers are moved into R8A779G0 V4H specific files, and the R8A78000 X5H files are added in parallel. The Gen5 DBSC driver is meant to be used in RSIP context, while the Gen4 DBSC driver is meant to be used in SPL, therefore the Kconfig conditionals have been adjusted to match. Signed-off-by: Marek Vasut

ram: renesas: rtvram: Add support for Renesas R-Car Gen5

2026-06-16T03:38:25Z

Add support for Renesas R-Car Gen5 R8A78000 SoC into RT-VRAM initialization driver. The changes are only a slight adjustment to the register programming, therefore reuse the existing RT-VRAM driver and parametrize those changes using driver data. Signed-off-by: Marek Vasut

ram: renesas: dbsc5: Fix off by 1 errors

2025-08-20T21:02:55Z

In dbsc5_read_vref_training the arrays dvw_min_byte0_table and dvw_min_byte1_table have 128 elements per channel. The variable vref_stop_index is limited to be a maximum of 128. This means that the index used to access the arrays must use a test of '< vref_stop_index' rather than '<= vref_stop_index' in order to prevent out of bounds accesses to the arrays. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Marek Vasut Tested-by: Marek Vasut

ram: renesas: dbsc5: Pass udevice and MODEMR0 to dbsc5_get_board_data()

2025-03-29T01:33:24Z

Pass DBSC5 udevice and MODEMR0 register values to board specific function dbsc5_get_board_data(). The board specific implementation of dbsc5_get_board_data() can return struct renesas_dbsc5_board_config which matches the board based on the content of MODEMR0 or content of DT accessible via the udevice. Signed-off-by: Marek Vasut

ram: renesas: dbsc5: Factor out dbsc5_wait_dbwait()

2025-03-29T01:33:24Z

Extract wait for completion code from dbsc5_send_dbcmd2() into new separate function dbsc5_wait_dbwait(). This extracted code can be used to implement MR register read in the future. Signed-off-by: Marek Vasut

ram: renesas: dbsc5: Improve dbsc5_send_dbcmd2() signature

2025-03-29T01:33:24Z

Update dbsc5_send_dbcmd2() such that it takes multiple parameters instead of one magic register content value. These parameters are used to form the same resulting register value internally in the dbsc5_send_dbcmd2() function, but from well defined input constants. The new input constants are the operation code, channel, rank, and operation argument. The argument is operation code specific, therefore it is still a 16-bit magic number, but the rest of the arguments are now split up. No functional change. Signed-off-by: Marek Vasut

ram: renesas: dbsc5: Drop space before dbsc5_ddr_setval_all_ch()

2025-03-29T01:33:24Z

Remove leading space before dbsc5_ddr_setval_all_ch() , no functional change. Signed-off-by: Marek Vasut

ram: renesas: dbsc5: Clarify MR27/MR28/MR57 register operations

2025-03-29T01:33:24Z

Rename dbsc5_ddr_register_read() to dbsc5_ddr_register_mr27_mr57_read() and dbsc5_ddr_register_set() to dbsc5_ddr_register_mr28_set() to make it clear what those functions really do. No functional change. Signed-off-by: Marek Vasut

ram: renesas: dbsc5: Make struct renesas_dbsc5_board_config public

2025-03-16T13:56:16Z

Make struct renesas_dbsc5_board_config {} definition public via include/dbsc5.h, so this structure can be defined in board files and passed into the DBSC5 DRAM driver by overriding weak function dbsc5_get_board_data() on board level. Signed-off-by: Marek Vasut

ram: renesas: dbsc5: Add V4H-3/V4H-5/V4H-7 OTP based detection

2025-03-16T13:56:16Z

Add auto-detection and handling of Renesas R-Car V4H-3 and V4H-5 in addition to V4H-7 SoC variants based on OTP fuse programming. The V4H-3 and V4H-5 variants have reduced DRAM frequency options. Signed-off-by: Marek Vasut