u-boot.git/drivers/ram/rockchip, branch v2020.04

ram: rockchip: Fix Kconfig dependency for RAM_ROCKCHIP_DEBUG

2020-02-13T15:10:50Z

There is no reason to show RAM_ROCKCHIP_DEBUG entry in other .config files as I see it for Xilinx ZynqMP. \# CONFIG_U_QE is not set \# CONFIG_RAM is not set CONFIG_RAM_ROCKCHIP_DEBUG=y Add missing dependency on RAM_ROCKCHIP driver. Signed-off-by: Michal Simek

dm: core: Require users of devres to include the header

2020-02-06T02:33:46Z

At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass Reviewed-by: Anatolij Gustschin

ram: rk3328: only do data traning for cs0

2020-01-30T03:44:01Z

No need to do twice data training for rk3328 ddr sdram, we re-use the setting for both channel. And adjust the sdram_init properly for correct init flow. Signed-off-by: Kever Yang Signed-off-by: YouMin Chen

arm: rockchip: Add common cru.h

2020-01-30T03:44:01Z

Few of the rockchip family SoC atleast rk3288, rk3399 are sharing some cru register bits so adding common code between these SoC families would require to include both cru include files that indeed resulting function declarations error. So, create a common cru include as cru.h then include the rk3399 arch cru include file and move the common cru register bit definitions into it. The rest of rockchip cru files will add it in future. Reviewed-by: Kever Yang Signed-off-by: Jagan Teki

ram: rk3399: don't assume phy_io_config() uses real regs

2020-01-30T03:44:01Z

In the RK3399 DRAM driver, the function set_ds_odt() supports operating in two different modes, selected by the ctl_phy_reg argument: when true, the function reads and writes directly from the DRAM registers, accessed through "chan->pctl->denali_*"; when false, the function reads and writes from an array, accessed through "params->pctl_regs.denali_*", which is written to DRAM registers at a later time. However, phy_config_io(), which is called by set_ds_odt() to do a subset of its register operations, operates directly on DRAM registers at all times. This means that it reads incorrect values (and writes new values prematurely) when ctl_phy_reg in set_ds_odt() is false. Fix this by passing in the address of the registers to work with. This prevents an "Invalid DRV value" error in the SPL debug log and (presumably) results in a more correct end state. See the following logs from a RK3399 NanoPi M4 board (4GB LPDDR3): Before: sdram_init() Starting SDRAM initialization... phy_io_config() Invalid DRV value. phy_io_config() Invalid DRV value. sdram_init() sdram_init: data trained for rank 2, ch 0 phy_io_config() Invalid DRV value. phy_io_config() Invalid DRV value. sdram_init() sdram_init: data trained for rank 2, ch 1 Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride 256B stride sdram_init() Finish SDRAM initialization... After: sdram_init() Starting SDRAM initialization... sdram_init() sdram_init: data trained for rank 2, ch 0 sdram_init() sdram_init: data trained for rank 2, ch 1 Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride 256B stride sdram_init() Finish SDRAM initialization... Signed-off-by: Thomas Hebb Reviewed-by: Kever Yang

common: Move hang() to the same header as panic()

2020-01-17T22:53:40Z

At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass [trini: Migrate a few more files] Signed-off-by: Tom Rini

rockchip: rk3308: Add sdram driver

2019-11-17T09:22:53Z

A dm based dram driver for rk3308 u-boot to get capacity. Signed-off-by: Andy Yan Reviewed-by: Kever Yang

ram: rk3399: Fix dram setting to make dram more stable

2019-11-17T08:23:56Z

There are some code different with rockchip vendor code which may lead to different bugs, including: 1) Fix setting error about LPDDR3 dram size ODT. 2) Set phy io speed to 0x2. 3) Fix setting error about phy_pad_fdbk_drive. 4) Fix setting error about PI_WDQLVL_VREF_EN Signed-off-by: YouMin Chen Signed-off-by: Kever Yang

ram: rk3399: update calculate_stride

2019-11-17T08:23:56Z

Update the calculation of the stride to support all the DRAM case. Signed-off-by: YouMin Chen Signed-off-by: Kever Yang

ram: rk3399: Sync the io setting from Rockchip vendor code

2019-11-17T08:23:56Z

The io setting are updated after some bugfix in different rk3399 boards, sync the code from vendor. Signed-off-by: YouMin Chen Signed-off-by: Kever Yang