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<title>u-boot.git/drivers/ram/rockchip, branch v2023.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ram/rockchip?h=v2023.07</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/ram/rockchip?h=v2023.07'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2023-05-06T09:28:18Z</updated>
<entry>
<title>core: remap: fix regmap_init_mem_plat() reg size handeling</title>
<updated>2023-05-06T09:28:18Z</updated>
<author>
<name>Johan Jonker</name>
<email>jbx6244@gmail.com</email>
</author>
<published>2023-03-13T00:30:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0fbb96964b8574ca8012b2022cd0e431977fd340'/>
<id>urn:sha1:0fbb96964b8574ca8012b2022cd0e431977fd340</id>
<content type='text'>
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so convert regmap_init_mem_plat() input to handel both. The
syscon class driver also makes use of the regmap_init_mem_plat()
function, but has no way of knowing the format of the
device-specific platform data. In case of odd reg structures other
then that the syscon class driver assumes the regmap must be
filled in the individual syscon driver before pre-probe.
Also fix the ARRAY_SIZE divider in the syscon class driver.

Signed-off-by: Johan Jonker &lt;jbx6244@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>ram: rk3399: add missing high row detection</title>
<updated>2023-04-21T07:16:01Z</updated>
<author>
<name>Jonathan Liu</name>
<email>net147@gmail.com</email>
</author>
<published>2023-03-23T10:35:58Z</published>
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<id>urn:sha1:cf8b415d5cdf11d30eb619e1972ef7a6b4e315e2</id>
<content type='text'>
For 2 GB LPDDR4 single-rank RAM with 16 rows, the Rockchip ddr init bin
prints:
"Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB"

U-Boot TPL prints:
"BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB"

Add missing high row detection so that U-Boot TPL prints Row=16, same as
the Rockchip ddr init bin:
"BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB"

Signed-off-by: Jonathan Liu &lt;net147@gmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>rockchip: Fix incorrect constant name in RAM init code</title>
<updated>2023-04-02T16:57:12Z</updated>
<author>
<name>David Sebek</name>
<email>dasebek@gmail.com</email>
</author>
<published>2023-03-30T21:51:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=86169cdcb0ec53c93e27f7a6c983c33862a1f616'/>
<id>urn:sha1:86169cdcb0ec53c93e27f7a6c983c33862a1f616</id>
<content type='text'>
A condition in the rk3399 RAM initialization code used the old
CONFIG_RAM_RK3399_LPDDR4 constant name. This commit changes the
condition to use the correct CONFIG_RAM_ROCKCHIP_LPDDR4 constant.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>ram: rockchip: Add rk3588 ddr driver support</title>
<updated>2023-02-28T10:07:27Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2023-01-30T14:57:38Z</published>
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<id>urn:sha1:3b7f29f2c8b6d4f1ad52fb98b22a5f8529a3a1ba</id>
<content type='text'>
Add ddr driver for rk3588 to get the ram capacity.

Co-developed-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>global: Finish CONFIG -&gt; CFG migration</title>
<updated>2023-01-20T17:27:24Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-01-10T16:19:45Z</published>
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<id>urn:sha1:6e7df1d151a7a127caf3b62ff6dfc003fc2aefcd</id>
<content type='text'>
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks.  Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>ram: rockchip: Add rv1126 lpddr4 support</title>
<updated>2023-01-16T10:01:11Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:50:55Z</published>
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<id>urn:sha1:0900840b4668d4b8bd9d22f2b8108d9c3698caf2</id>
<content type='text'>
Add LPDDR4 detection timings and support for RV1126.

Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>ram: rockchip: rv1126: Control ddr init prints via DEBUG</title>
<updated>2023-01-16T10:01:10Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:50:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4fadeecb62e201ecea53380964794bf7546f14cf'/>
<id>urn:sha1:4fadeecb62e201ecea53380964794bf7546f14cf</id>
<content type='text'>
Control the ddr init print messages via RAM_ROCKCHIP_DEBUG
instead of printing by default.

This gives an option to configs to enable these prints or
not.

Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>ram: rockchip: Add rv1126 ddr driver support</title>
<updated>2023-01-16T10:01:10Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:50:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e869b3485cf56aa4d29d18b83b589afde1672814'/>
<id>urn:sha1:e869b3485cf56aa4d29d18b83b589afde1672814</id>
<content type='text'>
Add DDR driver for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen &lt;cym@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>ram: rockchip: Add rv1126 ddr loader params</title>
<updated>2023-01-16T10:01:10Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:50:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a70a62cd529b681650e980b7f143cb4d3d2824ba'/>
<id>urn:sha1:a70a62cd529b681650e980b7f143cb4d3d2824ba</id>
<content type='text'>
Add DDR loader parameters for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen &lt;cym@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>ram: rockchip: Add rv1126 ddr3 support</title>
<updated>2023-01-16T10:01:10Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:50:51Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d04aa29fbab60ead930040fb9b989958097d6aa0'/>
<id>urn:sha1:d04aa29fbab60ead930040fb9b989958097d6aa0</id>
<content type='text'>
Add DDR3 detection timings for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen &lt;cym@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
</feed>
