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<title>u-boot.git/drivers/ram, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ram?h=master</id>
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<updated>2026-06-29T21:29:56Z</updated>
<entry>
<title>Merge patch series "arm: aspeed: add initial AST2700 SoC support"</title>
<updated>2026-06-29T21:29:56Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-06-29T19:44:52Z</published>
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<id>urn:sha1:0d8e33717d7e5b2a4034cc88f18bf233f77801e7</id>
<content type='text'>
Ryan Chen &lt;ryan_chen@aspeedtech.com&gt; says:

AST2700 is the 8th generation of Integrated Remote Management
Processor introduced by ASPEED Technology Inc. It is a Board
Management Controller (BMC) SoC family with a dual-die architecture:
SoC0 ("CPU" die with four ARM Cortex-A35 application cores) and
SoC1 ("IO" die with peripherals) each SoC have its own SCU PLLs,
clock dividers and reset domains.

Link: https://lore.kernel.org/r/20260612-ast2700_clk-v4-0-9bea29cfdc39@aspeedtech.com
</content>
</entry>
<entry>
<title>ram: aspeed: add SDRAM controller driver for AST2700</title>
<updated>2026-06-29T19:43:21Z</updated>
<author>
<name>Ryan Chen</name>
<email>ryan_chen@aspeedtech.com</email>
</author>
<published>2026-06-12T09:43:13Z</published>
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<id>urn:sha1:4a72fd9fb09109857303ca64fd259009e1d4b554</id>
<content type='text'>
Add a SDRAM controller driver for the AST2700, derived from the
existing AST2700 controller code used by the Ibex SPL but adapted
to run from ARM U-Boot proper on the Cortex-A35 cores.

The DDR4/DDR5 controller and its DesignWare PHY are programmed by
the Ibex SPL before ARM U-Boot proper takes over. This driver
reads back the configuration left by the SPL, probes the
controller, and exposes ram_info (base and size, with the VGA
carve-out subtracted) via UCLASS_RAM so that dram_init() can
populate gd-&gt;ram_size.

The PHY firmware-load entry points (dwc_ddrphy_phyinit_userCustom_*)
are kept compiled but call a __weak fmc_hdr_get_prebuilt() stub
when ARM U-Boot proper is the caller; the real implementation is
provided by the Ibex SPL via the same fmc_hdr.h descriptor format
(here added for the ARM build).

Adds the supporting register-layout headers under
arch/arm/include/asm/arch-aspeed/:
  - sdram.h:   SDRAM controller and DWC PHY register definitions
  - scu.h:     SCU bits referenced by the SDRAM driver
  - fmc_hdr.h: prebuilt-blob descriptor (binary-compatible with
               arch/riscv/include/asm/arch-ast2700/fmc_hdr.h used
               by the Ibex SPL)

Signed-off-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>Kconfig: drivers: restyle remaining</title>
<updated>2026-06-25T21:00:58Z</updated>
<author>
<name>Johan Jonker</name>
<email>jbx6244@gmail.com</email>
</author>
<published>2026-06-10T14:41:21Z</published>
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<id>urn:sha1:145d58e2c7276f68195a7fc760457a5b88f867dd</id>
<content type='text'>
Restyle all Kconfigs for the rest of "drivers":
Menu entries   : no space left
Menu attributes: 1 TAB
Help text      : 1 TAB + 2 spaces
Replace '---help---' by 'help'

Signed-off-by: Johan Jonker &lt;jbx6244@gmail.com&gt;
[trini: Add missing indentation on a few more multi-paragraph help texts]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v2026.07-rc5' into next</title>
<updated>2026-06-22T22:42:41Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-06-22T22:42:41Z</published>
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<id>urn:sha1:9f16b258e5632d74fa4a1c2c93bea4474e05234b</id>
<content type='text'>
Prepare v2026.07-rc5
</content>
</entry>
<entry>
<title>ram: renesas: dbsc5: Add Renesas R-Car Gen5 DBSC5 driver</title>
<updated>2026-06-16T03:38:25Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2026-06-10T18:20:58Z</published>
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<id>urn:sha1:a06d8334e5f4cd31392e13a168b20a95139b2f18</id>
<content type='text'>
Add Renesas R-Car Gen5 DBSC5 DRAM controller driver. This driver is currently
capable of bringing LPDDR5X DRAM on Renesas R-Car X5H Ironhide board. Further
boards can be supported by supplying board specific DRAM configuration data
via dbsc5_get_board_data().

The driver reuses parts of previous DBSC5 driver, but due to hardware changes,
can not be fully integrated into existing DBSC and DRAM driver, therefore the
currentl DBSC and DRAM drivers are moved into R8A779G0 V4H specific files, and
the R8A78000 X5H files are added in parallel.

The Gen5 DBSC driver is meant to be used in RSIP context, while the Gen4 DBSC
driver is meant to be used in SPL, therefore the Kconfig conditionals have been
adjusted to match.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>ram: renesas: rtvram: Add support for Renesas R-Car Gen5</title>
<updated>2026-06-16T03:38:25Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2026-06-10T18:20:57Z</published>
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<id>urn:sha1:93e5ca926101b3ffabfbff25057a38fd17ff9ea0</id>
<content type='text'>
Add support for Renesas R-Car Gen5 R8A78000 SoC into RT-VRAM
initialization driver. The changes are only a slight adjustment
to the register programming, therefore reuse the existing RT-VRAM
driver and parametrize those changes using driver data.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>ram: aspeed: Use dev_read_addr_x() API</title>
<updated>2026-06-09T20:53:34Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2026-05-25T04:07:41Z</published>
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<id>urn:sha1:d26cbf4667c9b8193b06c6f8e9fa7334866c94ac</id>
<content type='text'>
Use dev_read_addr_ptr() and dev_read_addr_index_ptr() which support both
live device tree and flat DT backends, avoiding direct dependency on
devfdt_* helpers.

While at here, also use ofnode_read_s32_default() to replace
fdtdec_get_int().

No functional changes.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-rockchip-20260309' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next</title>
<updated>2026-03-10T16:07:04Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-03-10T14:17:13Z</published>
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<id>urn:sha1:d93a63acfe701aa07c9223ec454164c88e7eb43d</id>
<content type='text'>
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/29452

- New SoC support: RK3506, RK3582;
- New Board support: RK3528 FriendlyElec NanoPi Zero2;
- Other fixes
</content>
</entry>
<entry>
<title>ram: rockchip: Add basic support for RK3506</title>
<updated>2026-03-10T16:07:03Z</updated>
<author>
<name>Jonas Karlman</name>
<email>jonas@kwiboo.se</email>
</author>
<published>2026-01-31T23:38:15Z</published>
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<id>urn:sha1:05b8228648f27153a3cee025f9024aa9b1281ce0</id>
<content type='text'>
Add support for reading DRAM size information from PMUGRF os_reg2 reg.

Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Tested-by: Aaron Griffith &lt;aargri@gmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>treewide: Clean up DECLARE_GLOBAL_DATA_PTR usage</title>
<updated>2026-02-17T19:50:22Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2026-02-09T01:30:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0f90b1e715f8abe41b0875752eb184f46032ff11'/>
<id>urn:sha1:0f90b1e715f8abe41b0875752eb184f46032ff11</id>
<content type='text'>
Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.

Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.

Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt; #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal &lt;anshuld@ti.com&gt; #TI boards
Acked-by: Yao Zi &lt;me@ziyao.cc&gt; #TH1520
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
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