u-boot.git/drivers/ram, branch v2017.09

ram: kconfig: s/SPL/TPL/ in TPL_RAM help text

2017-08-26T18:56:06+00:00

Signed-off-by: Jagan Teki

rockchip: rk3368: add DRAM controller driver with DRAM initialisation

2017-08-13T15:12:33+00:00

This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported:
 - DDR3
 - 32-bit configuration (i.e. fully populated)
 - dual-rank (i.e. no auto-detection of ranks)
 - DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to
the RK3368 BROM.  It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).

Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).

The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block.  This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass

spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)

2017-08-13T15:12:20+00:00

To allow finer grained selection of features for TPL, we introduce
TPL_RAM (in analogy to SPL_RAM).

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini

spl: dm: Kconfig: SPL_RAM depends on SPL_DM

2017-08-13T15:12:20+00:00

This commit models the dependency from SPL_RAM to SPL_DM in Kconfig.

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini

ram: stm32: add stm32h7 support

2017-07-26T15:29:15+00:00

STM32F7 and H7 shared the same SDRAM control block.
On STM32H7 few control bits has been added.
The current driver need some minor adaptation as FMC block
enable/disable for H7.

Signed-off-by: Patrice Chotard

ram: stm32: add second SDRAM bank management

2017-07-26T15:29:15+00:00

FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.

Even if only bank2 is used, some bank1 registers must be
configured.

Signed-off-by: Patrice Chotard 
Reviewed-by: Simon Glass

ram: stm32: replace fdtdec_get by ofnode calls

2017-07-26T15:29:14+00:00

Replace all fdtdec_get..() calls by ofnode_read...() or dev_read..().
This will allow drivers to support a live device tree.

Signed-off-by: Patrice Chotard 
Reviewed-by: Simon Glass

ram: stm32: get base address from DT

2017-07-26T15:29:14+00:00

Retrieve RAM base address from DT instead of using STM32_SDRAM_FMC

For STM32F7, FMC block base address is 0xA0000000, but SDRAM
registers are located at offset 0x140 inside FMC block.
Update the stm32_fmc_regs fields with all FMC registers
to map SDRAM registers at the right address.

These additionals registers will be used later.

Signed-off-by: Patrice Chotard

ram: stm32: migrate fmc defines in driver file

2017-07-26T15:29:07+00:00

Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h
to drivers/ram/stm32_sdram.c

This will avoid to add an additionnal arch-stm32xx/fmc.h file when
a new stm32 family soc will be introduced.

Signed-off-by: Patrice Chotard 
Reviewed-by: Vikas Manocha 
Reviewed-by: Simon Glass

drivers: ram: stm32: fix compilation issue

2017-06-05T18:13:13+00:00

If CONFIG_CLK flag is not set, compilation raises the
following error message:

drivers/ram/stm32_sdram.c: In function 'stm32_fmc_probe':
drivers/ram/stm32_sdram.c:154:2: error: 'ret' undeclared (first use in this function)
  ret = stm32_sdram_init(dev);

Signed-off-by: Patrice Chotard 
cc: Vikas Manocha