u-boot.git/drivers/ram, branch v2019.10

ram: rk3288: Initialize dram for TPL builds

2019-09-19T01:35:31+00:00

Few of the rk3288 boards like tinker, vyasa are using
TPL, SPL bootchain so the dram initialization must needed
during TPL stage. So add proper ifconstruct to satisfy
both TPL, SPL and SPL-only bootchain boards.

This eventually fixing TPL to SPL handoff, otherwise missing
dram initilaztion at TPL stage would leads to SPL hang.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang

stm32mp1: ram: add pattern parameter in infinite write test

2019-08-27T09:19:23+00:00

Add pattern for infinite test_read and test_write, that
allow to change the pattern to test without recompilation;
default pattern is 0xA5A5AA55.

Signed-off-by: Patrick Delaunay

stm32mp1: ram: reload watchdog during ddr test

2019-08-27T09:19:23+00:00

Avoid watchdog during infinite DDR test.

Signed-off-by: Patrick Delaunay

stm32mp1: ram: update loop management in infinite test

2019-08-27T09:19:23+00:00

Reduce verbosity of the infinite tests to avoid CubeMX issue.
test and display loop by 1024*1024 accesses: read or write.

Signed-off-by: Patrick Delaunay

stm32mp1: ram: fix address issue in 2 tests

2019-08-27T09:19:23+00:00

If user choose to test memory size is 1GByte (0x40000000),
memory address would overflow in test "Random" and
test "FrequencySelectivePattern".
Thus the system would hangs up when running DDR test.

Signed-off-by: Patrick Delaunay 
Signed-off-by: Bossen WU

stm32mp1: ram: cosmetic: remove unused prototype

2019-08-27T09:19:23+00:00

Signed-off-by: Patrick Delaunay

ram: rk3399: update cap and ddrconfig for each channel after init

2019-08-23T07:27:40+00:00

We need to store all the ram related cap/map info back to register
for each channel after all the init has been done in case some of register
was reset during the process.

Signed-off-by: YouMin Chen 
Signed-off-by: Kever Yang

rockchip: ram: add full feature rk3328 DRAM driver

2019-08-05T13:14:45+00:00

This driver supports DDR3/LPDDR3/DDR4 SDRAM initialization.

Signed-off-by: YouMin Chen 
Signed-off-by: Kever Yang 
[cherry picked from commit https://github.com/rockchip-linux/u-boot/commit/9fb0777ec3cc6a89af9d2e0969c3bfe58306a88d with minor modifications]
Signed-off-by: Matwey V. Kornilov 
Reviewed-by: Kever Yang

rockchip: rk322x: sdram: use udelay instead of rockchip_udelay

2019-07-20T15:59:44+00:00

Use system api for udelay instead of vendor defined api,
and rockchip_udelay() will be removed.

Signed-off-by: Kever Yang

ram: rk3399: Add lpddr4 set rate support

2019-07-20T15:59:44+00:00

Unlike rest of dram type chips, LPDDR4 initialization start
with at board selected frequency (say 50MHz) and then it
switches into 400MHz and 800MHz simultaneously to make the
proper sequence work on each channel with associated training.

The lpddr4 set rate sequnce will follow by setting lpddr4
- dq out
- ca odt
- MR3
- MR12
- MR14
registers sets in sequential order.

Here is sameple log about LPDDR4-100 init sequence in Rockpro64:

Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
channel 0 training pass
channel 1 training pass
change freq to 400 MHz 0, 1
channel 0 training pass
channel 1 training pass
change freq to 800 MHz 1, 0

This patch add support to this init sequence via lpddr4 set rate
by taking sdram timing parameters from 400, 800 .inc files.

Signed-off-by: Jagan Teki 
Signed-off-by: YouMin Chen 
Reviewed-by: Kever Yang 
(Fix travis error, use one ret instead of ret[2] in set_ctrl)
Signed-off-by: Kever Yang