u-boot.git/drivers/ram, branch v2019.10-rc2

rockchip: ram: add full feature rk3328 DRAM driver

2019-08-05T13:14:45Z

This driver supports DDR3/LPDDR3/DDR4 SDRAM initialization. Signed-off-by: YouMin Chen Signed-off-by: Kever Yang [cherry picked from commit https://github.com/rockchip-linux/u-boot/commit/9fb0777ec3cc6a89af9d2e0969c3bfe58306a88d with minor modifications] Signed-off-by: Matwey V. Kornilov Reviewed-by: Kever Yang

rockchip: rk322x: sdram: use udelay instead of rockchip_udelay

2019-07-20T15:59:44Z

Use system api for udelay instead of vendor defined api, and rockchip_udelay() will be removed. Signed-off-by: Kever Yang

ram: rk3399: Add lpddr4 set rate support

2019-07-20T15:59:44Z

Unlike rest of dram type chips, LPDDR4 initialization start with at board selected frequency (say 50MHz) and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. The lpddr4 set rate sequnce will follow by setting lpddr4 - dq out - ca odt - MR3 - MR12 - MR14 registers sets in sequential order. Here is sameple log about LPDDR4-100 init sequence in Rockpro64: Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride channel 0 training pass channel 1 training pass change freq to 400 MHz 0, 1 channel 0 training pass channel 1 training pass change freq to 800 MHz 1, 0 This patch add support to this init sequence via lpddr4 set rate by taking sdram timing parameters from 400, 800 .inc files. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang (Fix travis error, use one ret instead of ret[2] in set_ctrl) Signed-off-by: Kever Yang

ram: rk3399: Add set_rate sdram rk3399 ops

2019-07-20T16:00:32Z

DDR set rate can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4. For this requirement, and for code readability handle data training via sdram_rk3399_ops with .set_rate and same will update in future while supporting lpddr4 code. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang

ram: rk3399: Add LPPDDR4-800 timings inc

2019-07-20T16:00:30Z

LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. So, add LPDDR4-800 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang

ram: rk3399: Add LPPDDR4-400 timings inc

2019-07-20T16:00:27Z

LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. So, add LPDDR4-400 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang

ram: rk3399: Add LPPDR4 mr detection

2019-07-20T16:00:10Z

Like data training in other sdram types, mr detection need to taken care for lpddr4 with looped rank and associated channel to make sure the proper configuration held. Once the mr detection successful for active and configured rank with channel number, the same can later reused during actual LPDDR4 initialization. So, add code to support for it. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang

ram: rk3399: Handle data training via ops

2019-07-20T16:00:07Z

data training can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4. For this requirement, and for code readability handle data training via sdram_rk3399_ops and same will update in future while supporting lpddr4 code. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang

ram: rk3399: Simplify data training first argument

2019-07-20T16:00:01Z

data training is using chan_info as first argument with channel number as second argument instead of that use dram_info as first argument so-that we can get the chan_info at data training definition. This was the argument handling is meaningful, readable and it would help to add similar data training for lpddr4 in future. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang

ram: rk3399: Update lpddr4 vref_mode_ac

2019-07-20T15:59:44Z

Update vref_mode_ac for lpddr4 based on VDDQ/3/2=16.8% Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang