u-boot.git/drivers/ram, branch v2020.07-rc2

configs: stm32mp1: replace STM32MP1_TRUSTED by TFABOOT

2020-04-15T07:08:37Z

Activate ARCH_SUPPORT_TFABOOT and replace the arch stm32mp specific config CONFIG_STM32MP1_TRUSTED by the generic CONFIG_TFABOOT introduced by the commit 535d76a12150 ("armv8: layerscape: Add TFABOOT support"). This config CONFIG_TFABOOT is activated for the trusted boot chain, when U-Boot is loaded by TF-A. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard

ram: stm32mp1: the property st, phy-cal becomes optional

2020-03-24T13:23:30Z

This parameter "st,phy-cal" becomes optional and when it is absent the built-in PHY calibration is done. It is the case in the helper dtsi file "stm32mp15-ddr.dtsi" except if DDR_PHY_CAL_SKIP is defined. This patch also impact the ddr interactive mode - the registers of the param 'phy.cal' are initialized to 0 when "st,phy-cal" is not present in device tree (default behavior when DDR_PHY_CAL_SKIP is not activated) - the info 'cal' field can be use to change the calibration behavior - cal=1 => use param phy.cal to initialize the PHY, built-in training is skipped - cal=0 => param phy.cal is absent, built-in training is used (default) Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard

ram: stm32mp1: reduce delay after BIST reset for tuning

2020-03-24T13:23:26Z

Reduce the delay after BIST delay, from 1ms to 10us which is enough accoriding datasheet. Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard

ram: stm32mp1_ddr: fix self refresh disable during DQS training

2020-03-24T13:23:18Z

DDRCTRL_PWRCTL.SELFREF_EN needs to be reset before DQS training step, not to enter in self refresh mode during the execution of this phase. Depending on settings, it can be set after the DQS training. Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard

ram: stm32mp1: update BIST config for tuning

2020-03-24T13:20:50Z

Update the BIST config to compute the real use mask for the real bank, row and col of the used DDR. The values are get from addrmap register value. Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard

ram: stm32mp1: tuning: deactivate derating during BIST test

2020-03-24T13:20:50Z

The derating (timing parameter derating using MR4 read value) can't be activated during BIST test, as the MR4 read answer will be not understood by BIST (BISTGSR.BDONE bit stay at 0, BISTWCSR.DXWCNT = 0x206 instead of BISTWCR.BWCNT = 0x200). This patch only impacts the tuning on LPDDR2/LPDDR3, if derateen.derate_enable = 1. Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard

ram: stm32mp1: tuning: add timeout for polling BISTGSR.BDDONE

2020-03-24T13:20:50Z

Avoid to block the tuning procedure on BIST error (not finished BIST procedure) by adding a 1000us timeout on the polling of BISTGSR.BDDONE executed to detect the end of BIST. The normal duration of the BIST test is around 5us. This patch also cleanup comments. Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard

ram: stm32mp1: don't display the prompt two times

2020-03-24T13:20:50Z

Remove one "DDR>" display on command - next - step - go Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard

ram: stm32mp1: display result for software read DQS gating

2020-03-24T13:20:50Z

Display result information for software read DQS gating, the tuning 0 which be used by CubeMX DDR tuning tools. Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard

ram: stm32mp1: increase vdd2_ddr: buck2 for 32bits LPDDR

2020-03-24T13:20:50Z

Need to increase the LPDDR2/LPDDR3 the voltage vdd2_ddr: buck2 form 1.2V to 1.25V for 32bits configuration. Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard