u-boot.git/drivers/ram, branch v2022.04-rc2

ram: k3-ddrss: Add support for J721S2 SoC

2022-02-08T14:41:27Z

Add support for DDR subsystem in J721S2 SoC. Signed-off-by: David Huang Signed-off-by: Aswath Govindraju

ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems

2022-02-08T14:41:26Z

In Multi DDR subystems with interleaving support, the following needs to configured, - interleaving granular size and region - EMIFs to be enabled - EMIFs with ecc to be enabled - EMIF separated or interleaved - number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port, by default set to 3 Add support for configuring all the above by using a MSMC device Signed-off-by: Aswath Govindraju

ram: k3-ddrss: Add support for multiple instances of DDR subsystems

2022-02-08T14:41:26Z

The current driver only supports single instance of DRR subsystem. Add support for probing multiple instances of DDR subsystem. Signed-off-by: Aswath Govindraju

ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance

2022-02-08T14:41:26Z

Add a pointer to ddr instance int the lpddr4_privatedata_s structure for supporting mutliple instances of DDR in the drivers. Signed-off-by: Aswath Govindraju

drivers: octeon: get rid of Unicode in code

2022-01-20T13:45:46Z

Placing Unicode control codes in the middle of a comment does not make much sense. Let's get rid of all Unicode in drivers/ram/octeon/octeon3_lmc.c. Signed-off-by: Heinrich Schuchardt Reviewed-by: Stefan Roese

ram: stm32mp1: remove __maybe_unused on stm32mp1_ddr_setup

2021-11-30T15:43:28Z

Since the commit f42045b2e750 ("stm32mp15: replace CONFIG_TFABOOT when it is possible") the function stm32mp1_ddr_setup is always called so the __maybe_unused can be removed. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard

ram: stm32mp1: compute DDR size from DDRCTL registers

2021-11-30T15:43:28Z

Compute the DDR size from DDR controller register (mstr and addrmap) in U-Boot proper as the DDR information are useful only for SPL but not for U-Boot proper, for example with TFABOOT. This patch simplify U-Boot DT when several DDR size are supported and support of next SOC in STM32MP family. Signed-off-by: Patrick Delaunay Signed-off-by: Patrick Delaunay

stm32mp1: ram: remove tuning support

2021-11-30T15:43:28Z

Remove the DDR interactive command tuning, as the support of a predefined DDR PHY tuning is removed for STM32MP1 driver in SPL and in TF-A and the result of this tuning will be never used. Moreover this SW tuning procedure can failed on some hardware configuration (to many BIST errors and no convergence); it will be no more supported in the next delivery of the DDR utilities included in the CubeMX tool of STMicroelectronics. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard

stm32mp1: ram: remove the support of calibration result

2021-11-30T15:43:28Z

The support of a predefined DDR PHY tuning result is removed for STM32MP1 driver because it is not needed at the supported frequency when built-in calibration is executed. The calibration parameters were provided in the device tree by the optional node "st,phy-cal", activated in ddr helper file by the compilation flag DDR_PHY_CAL_SKIP and filled with values generated by the CubeMX DDR utilities. This patch - updates the binding file to remove "st,phy-cal" support - updates the device trees and remove the associated defines - simplifies the STM32MP1 DDR driver and remove the support of the optional parameter "st,phy-cal" After this patch, the built-in calibration is always executed and the calibration registers are moved in the phy dynamic part; that allows manual tests. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard

stm32mp1: ram: add read valid training support

2021-11-30T15:43:28Z

Add the read data eye training = training for optimal read valid placement (RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3. This training is supported on the PUBL integrated in the STM32MP15x DDR subsystem and it is not required for DDR3. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard