u-boot.git/drivers/ram, branch v2022.10-rc2

arm: mach-k3: Rename SOC_K3_AM6 to SOC_K3_AM654

2022-07-25T17:02:04Z

The first AM6x device was the AM654x, but being the first we named it just AM6, since more devices have come out with this same prefix we should switch it to the normal convention of using the full name of the first compatibility device the series. This makes what device we are talking about more clear and matches all the K3 devices added since. Signed-off-by: Andrew Davis Reviewed-by: Tom Rini

tpl: Ensure all TPL symbols in Kconfig have some TPL dependency

2022-06-28T21:03:31Z

Tighten up symbol dependencies in a number of places. Ensure that a TPL specific option has at least a direct dependency on TPL. In places where it's clear that we depend on something more specific, use that dependency instead. Reported-by: Pali Rohár Signed-off-by: Tom Rini

ram: stm32mp1: add support of STM32MP13x

2022-06-17T08:41:16Z

Add support for new compatible "st,stm32mp13-ddr" to manage the DDR sub system (Controller and PHY) in STM32MP13x SOC: - only one AXI port - support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2) The STM32MP15x SOC have 2 AXI ports and 32 bits support. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard

arm: mach-k3: Introduce the basic files to support AM62

2022-06-10T17:37:32Z

The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC architecture platform, providing ultra-low-power modes, dual display, multi-sensor edge compute, security and other BOM-saving integration. The AM62 SoC targets broad market to enable applications such as Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building Automation, Appliances and more. Some highlights of this SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Pin-to-pin compatible options for single and quad core are available. * Cortex-M4F for general-purpose or safety usage. * Dual display support, providing 24-bit RBG parallel interface and OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display resolution. * Selectable GPUsupport, up to 8GFLOPS, providing better user experience in 3D graphic display case and Android. * PRU(Programmable Realtime Unit) support for customized programmable interfaces/IOs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized System Controller for Security, Power, and Resource Management. * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, enabling battery powered system design. AM625 is the first device of the family. Add DT bindings for the same. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Suman Anna Signed-off-by: Gowtham Tammana Signed-off-by: Aswath Govindraju Signed-off-by: Nishanth Menon Signed-off-by: Vignesh Raghavendra Reviewed-by: Tom Rini

ram: stm32mp1: Conditionally enable ASR

2022-05-10T11:54:47Z

Enable DRAM ASR, auto self-refresh, conditionally, based on DT PWRCTL register bits. While ASR does save considerable amount of power at runtime automatically, it also causes LTDC underruns on large panels. Let user select whether or not ASR is required or not, generally ASR should be enabled on portable and battery operated devices. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrick Delaunay Signed-off-by: Patrice Chotard

ram: k3-ddrss: Allow use of dt provided initial frequency

2022-04-20T15:14:39Z

Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR frequency that is set for lpddr4 before initialization of the controller. Make this optional and continue to use PLL bypass frequency as is done currently if ti,ddr-freq0 is not provided. Signed-off-by: Dave Gerlach

ram: k3-ddrss: Fix register name and explain its usage

2022-04-20T15:14:39Z

The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect the maximum possible SDRAM of 2 GB for AM64x (instead of the register's default that says 8 GB, which the AM64x DDR controller wouldn't support). The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG was that of the next register at offset 0x24. Signed-off-by: Dominic Rath

rockchip: rk3066: add sdram driver

2022-04-18T03:25:13Z

Add rockchip rk3066 sdram driver Signed-off-by: Paweł Jarosz Signed-off-by: Johan Jonker Reviewed-by: Kever Yang

ram: k3-am654: Make VTT regulator optional

2022-04-04T23:02:04Z

Signed-off-by: Christian Gmeiner

ram: k3-am654: Write all configuration values

2022-04-04T23:02:04Z

Makes it possible to use 16-bit DDR memory. Signed-off-by: Dominic Rath Signed-off-by: Christian Gmeiner