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<title>u-boot.git/drivers/ram, branch v2023.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>rockchip: Fix incorrect constant name in RAM init code</title>
<updated>2023-04-02T16:57:12+00:00</updated>
<author>
<name>David Sebek</name>
<email>dasebek@gmail.com</email>
</author>
<published>2023-03-30T21:51:14+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=86169cdcb0ec53c93e27f7a6c983c33862a1f616'/>
<id>86169cdcb0ec53c93e27f7a6c983c33862a1f616</id>
<content type='text'>
A condition in the rk3399 RAM initialization code used the old
CONFIG_RAM_RK3399_LPDDR4 constant name. This commit changes the
condition to use the correct CONFIG_RAM_ROCKCHIP_LPDDR4 constant.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
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<pre>
A condition in the rk3399 RAM initialization code used the old
CONFIG_RAM_RK3399_LPDDR4 constant name. This commit changes the
condition to use the correct CONFIG_RAM_ROCKCHIP_LPDDR4 constant.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: rockchip: Add rk3588 ddr driver support</title>
<updated>2023-02-28T10:07:27+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2023-01-30T14:57:38+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3b7f29f2c8b6d4f1ad52fb98b22a5f8529a3a1ba'/>
<id>3b7f29f2c8b6d4f1ad52fb98b22a5f8529a3a1ba</id>
<content type='text'>
Add ddr driver for rk3588 to get the ram capacity.

Co-developed-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
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<pre>
Add ddr driver for rk3588 to get the ram capacity.

Co-developed-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>global: Finish CONFIG -&gt; CFG migration</title>
<updated>2023-01-20T17:27:24+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-01-10T16:19:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6e7df1d151a7a127caf3b62ff6dfc003fc2aefcd'/>
<id>6e7df1d151a7a127caf3b62ff6dfc003fc2aefcd</id>
<content type='text'>
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks.  Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks.  Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: rockchip: Add rv1126 lpddr4 support</title>
<updated>2023-01-16T10:01:11+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:50:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0900840b4668d4b8bd9d22f2b8108d9c3698caf2'/>
<id>0900840b4668d4b8bd9d22f2b8108d9c3698caf2</id>
<content type='text'>
Add LPDDR4 detection timings and support for RV1126.

Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add LPDDR4 detection timings and support for RV1126.

Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: rockchip: rv1126: Control ddr init prints via DEBUG</title>
<updated>2023-01-16T10:01:10+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:50:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4fadeecb62e201ecea53380964794bf7546f14cf'/>
<id>4fadeecb62e201ecea53380964794bf7546f14cf</id>
<content type='text'>
Control the ddr init print messages via RAM_ROCKCHIP_DEBUG
instead of printing by default.

This gives an option to configs to enable these prints or
not.

Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Control the ddr init print messages via RAM_ROCKCHIP_DEBUG
instead of printing by default.

This gives an option to configs to enable these prints or
not.

Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: rockchip: Add rv1126 ddr driver support</title>
<updated>2023-01-16T10:01:10+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:50:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e869b3485cf56aa4d29d18b83b589afde1672814'/>
<id>e869b3485cf56aa4d29d18b83b589afde1672814</id>
<content type='text'>
Add DDR driver for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen &lt;cym@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add DDR driver for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen &lt;cym@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: rockchip: Add rv1126 ddr loader params</title>
<updated>2023-01-16T10:01:10+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:50:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a70a62cd529b681650e980b7f143cb4d3d2824ba'/>
<id>a70a62cd529b681650e980b7f143cb4d3d2824ba</id>
<content type='text'>
Add DDR loader parameters for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen &lt;cym@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add DDR loader parameters for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen &lt;cym@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: rockchip: Add rv1126 ddr3 support</title>
<updated>2023-01-16T10:01:10+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:50:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d04aa29fbab60ead930040fb9b989958097d6aa0'/>
<id>d04aa29fbab60ead930040fb9b989958097d6aa0</id>
<content type='text'>
Add DDR3 detection timings for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen &lt;cym@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add DDR3 detection timings for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen &lt;cym@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: rockchip: Update ddr pctl regs for px30</title>
<updated>2023-01-16T10:01:10+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:50:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5ab30c3176bfda282d8e350c41d9731214eac582'/>
<id>5ab30c3176bfda282d8e350c41d9731214eac582</id>
<content type='text'>
Add full ddr pctl registers and bit masks for px30.

Signed-off-by: YouMin Chen &lt;cym@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add full ddr pctl registers and bit masks for px30.

Signed-off-by: YouMin Chen &lt;cym@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: rockchip: Compute ddr capacity based on grf split</title>
<updated>2023-01-16T10:01:10+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2022-12-14T17:50:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=29c31489743a92d8be9446afa778dde0ba702111'/>
<id>29c31489743a92d8be9446afa778dde0ba702111</id>
<content type='text'>
DDR chip capacity is computed based on GRF split in some
Rockchip SoC's like PX30 and RV1126.

Add split argument in ddr print info so-that the respective
ddr driver will pass the grf split.

Signed-off-by: YouMin Chen &lt;cym@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
DDR chip capacity is computed based on GRF split in some
Rockchip SoC's like PX30 and RV1126.

Add split argument in ddr print info so-that the respective
ddr driver will pass the grf split.

Signed-off-by: YouMin Chen &lt;cym@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
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