<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/ram, branch v2023.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>board: mediatek: update config headers</title>
<updated>2023-08-03T13:40:49+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2023-07-19T09:15:47+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fd9385abe29aa4ec92675e244275582271c17e02'/>
<id>fd9385abe29aa4ec92675e244275582271c17e02</id>
<content type='text'>
Remove unused information from include/configs/mtxxxx.h

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Remove unused information from include/configs/mtxxxx.h

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: k3-ddrss: do not touch ctrl regs during training</title>
<updated>2023-07-21T19:32:12+00:00</updated>
<author>
<name>Bryan Brattlof</name>
<email>bb@ti.com</email>
</author>
<published>2023-07-17T22:15:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=af7c33c103450e06aecf8adba8cbc8c522295be1'/>
<id>af7c33c103450e06aecf8adba8cbc8c522295be1</id>
<content type='text'>
During LPDDR initialization we will loop through a series of frequency
changes in order to train at the various operating frequencies. During
this training, accessing the DRAM_CLASS bitfield could happen during a
frequency change and cause the read to hang.

Store the DRAM type into the main structure to avoid multiple readings
while the independent phy is training.

Signed-off-by: Bryan Brattlof &lt;bb@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
During LPDDR initialization we will loop through a series of frequency
changes in order to train at the various operating frequencies. During
this training, accessing the DRAM_CLASS bitfield could happen during a
frequency change and cause the read to hang.

Store the DRAM type into the main structure to avoid multiple readings
while the independent phy is training.

Signed-off-by: Bryan Brattlof &lt;bb@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: starfive: Read memory size information from EEPROM</title>
<updated>2023-07-12T05:21:40+00:00</updated>
<author>
<name>Yanhong Wang</name>
<email>yanhong.wang@starfivetech.com</email>
</author>
<published>2023-06-15T09:36:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=38d900b409199df02a1a26dfcb464d4d2b6e27d2'/>
<id>38d900b409199df02a1a26dfcb464d4d2b6e27d2</id>
<content type='text'>
StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
DDR capacity includes 2G/4G/8G, a DT can not support multiple
capacities, so the capacity size information is recorded to EEPROM, when
DDR initialization required capacity size information is read from
EEPROM.

If there is no information in EEPROM, it is initialized with the default
size defined in DT.

Signed-off-by: Yanhong Wang &lt;yanhong.wang@starfivetech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
DDR capacity includes 2G/4G/8G, a DT can not support multiple
capacities, so the capacity size information is recorded to EEPROM, when
DDR initialization required capacity size information is read from
EEPROM.

If there is no information in EEPROM, it is initialized with the default
size defined in DT.

Signed-off-by: Yanhong Wang &lt;yanhong.wang@starfivetech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>board: schneider: add RZN1 board support</title>
<updated>2023-05-13T02:01:30+00:00</updated>
<author>
<name>Ralph Siemsen</name>
<email>ralph.siemsen@linaro.org</email>
</author>
<published>2023-05-13T01:36:56+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e87c869db3620c9b03b4364e144c19387d7bfd7a'/>
<id>e87c869db3620c9b03b4364e144c19387d7bfd7a</id>
<content type='text'>
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.

The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.

Signed-off-by: Ralph Siemsen &lt;ralph.siemsen@linaro.org&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.

The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.

Signed-off-by: Ralph Siemsen &lt;ralph.siemsen@linaro.org&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: cadence: add driver for Cadence EDAC</title>
<updated>2023-05-13T02:01:30+00:00</updated>
<author>
<name>Ralph Siemsen</name>
<email>ralph.siemsen@linaro.org</email>
</author>
<published>2023-05-13T01:36:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2d67a095dcfe249badb077874815fc0a225f9356'/>
<id>2d67a095dcfe249badb077874815fc0a225f9356</id>
<content type='text'>
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.

Signed-off-by: Ralph Siemsen &lt;ralph.siemsen@linaro.org&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.

Signed-off-by: Ralph Siemsen &lt;ralph.siemsen@linaro.org&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>core: remap: fix regmap_init_mem_plat() reg size handeling</title>
<updated>2023-05-06T09:28:18+00:00</updated>
<author>
<name>Johan Jonker</name>
<email>jbx6244@gmail.com</email>
</author>
<published>2023-03-13T00:30:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0fbb96964b8574ca8012b2022cd0e431977fd340'/>
<id>0fbb96964b8574ca8012b2022cd0e431977fd340</id>
<content type='text'>
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so convert regmap_init_mem_plat() input to handel both. The
syscon class driver also makes use of the regmap_init_mem_plat()
function, but has no way of knowing the format of the
device-specific platform data. In case of odd reg structures other
then that the syscon class driver assumes the regmap must be
filled in the individual syscon driver before pre-probe.
Also fix the ARRAY_SIZE divider in the syscon class driver.

Signed-off-by: Johan Jonker &lt;jbx6244@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so convert regmap_init_mem_plat() input to handel both. The
syscon class driver also makes use of the regmap_init_mem_plat()
function, but has no way of knowing the format of the
device-specific platform data. In case of odd reg structures other
then that the syscon class driver assumes the regmap must be
filled in the individual syscon driver before pre-probe.
Also fix the ARRAY_SIZE divider in the syscon class driver.

Signed-off-by: Johan Jonker &lt;jbx6244@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: mach-k3: Remove empty sys_proto.h include</title>
<updated>2023-04-24T17:18:48+00:00</updated>
<author>
<name>Andrew Davis</name>
<email>afd@ti.com</email>
</author>
<published>2023-04-06T16:38:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f392860c2e4bc5230742beccd86b7a8c72514350'/>
<id>f392860c2e4bc5230742beccd86b7a8c72514350</id>
<content type='text'>
This header file is now empty, remove it.

Signed-off-by: Andrew Davis &lt;afd@ti.com&gt;
Reviewed-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This header file is now empty, remove it.

Signed-off-by: Andrew Davis &lt;afd@ti.com&gt;
Reviewed-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: mach-k3: Move sdelay() and wait_on_value() declaration</title>
<updated>2023-04-24T17:18:48+00:00</updated>
<author>
<name>Andrew Davis</name>
<email>afd@ti.com</email>
</author>
<published>2023-04-06T16:38:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ef538cc26e490544d48084897472cbcee0430dde'/>
<id>ef538cc26e490544d48084897472cbcee0430dde</id>
<content type='text'>
These probably should be in some system wide header given their use.
Until then move them out of K3 sys_proto.h so we can finish cleaning
that header out.

Signed-off-by: Andrew Davis &lt;afd@ti.com&gt;
Reviewed-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
These probably should be in some system wide header given their use.
Until then move them out of K3 sys_proto.h so we can finish cleaning
that header out.

Signed-off-by: Andrew Davis &lt;afd@ti.com&gt;
Reviewed-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-rockchip-20230421' of https://source.denx.de/u-boot/custodians/u-boot-rockchip</title>
<updated>2023-04-23T16:15:56+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-04-23T16:15:56+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=328fdeb9c9a8178a262dcebb9991a2ffff5788b1'/>
<id>328fdeb9c9a8178a262dcebb9991a2ffff5788b1</id>
<content type='text'>
- Add rk3588 evb support;
- Update pinctrl for rk3568 and rk3588;
- Update rk3288 dts;
- Update mmc support for rk3568 and rk3588;
- Add rng support for rk3588;
- Add DSI support for rk3568;
- Some other misc fixes in dts, config, driver;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
- Add rk3588 evb support;
- Update pinctrl for rk3568 and rk3588;
- Update rk3288 dts;
- Update mmc support for rk3568 and rk3588;
- Add rng support for rk3588;
- Add DSI support for rk3568;
- Some other misc fixes in dts, config, driver;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge https://source.denx.de/u-boot/custodians/u-boot-riscv</title>
<updated>2023-04-22T22:31:46+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-04-22T22:31:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=802132c48a2e6b66ec83b7bb66fb96f2ba87c957'/>
<id>802132c48a2e6b66ec83b7bb66fb96f2ba87c957</id>
<content type='text'>
* Add StarFive VisionFive v2 Board support
* Support CONFIG_REMAKE_ELF
* Code cleanups for RISC-V architecture
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
* Add StarFive VisionFive v2 Board support
* Support CONFIG_REMAKE_ELF
* Code cleanups for RISC-V architecture
</pre>
</div>
</content>
</entry>
</feed>
