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<title>u-boot.git/drivers/ram, branch v2026.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/ram?h=v2026.07</id>
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<updated>2026-06-16T03:38:25Z</updated>
<entry>
<title>ram: renesas: dbsc5: Add Renesas R-Car Gen5 DBSC5 driver</title>
<updated>2026-06-16T03:38:25Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2026-06-10T18:20:58Z</published>
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<id>urn:sha1:a06d8334e5f4cd31392e13a168b20a95139b2f18</id>
<content type='text'>
Add Renesas R-Car Gen5 DBSC5 DRAM controller driver. This driver is currently
capable of bringing LPDDR5X DRAM on Renesas R-Car X5H Ironhide board. Further
boards can be supported by supplying board specific DRAM configuration data
via dbsc5_get_board_data().

The driver reuses parts of previous DBSC5 driver, but due to hardware changes,
can not be fully integrated into existing DBSC and DRAM driver, therefore the
currentl DBSC and DRAM drivers are moved into R8A779G0 V4H specific files, and
the R8A78000 X5H files are added in parallel.

The Gen5 DBSC driver is meant to be used in RSIP context, while the Gen4 DBSC
driver is meant to be used in SPL, therefore the Kconfig conditionals have been
adjusted to match.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>ram: renesas: rtvram: Add support for Renesas R-Car Gen5</title>
<updated>2026-06-16T03:38:25Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2026-06-10T18:20:57Z</published>
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<id>urn:sha1:93e5ca926101b3ffabfbff25057a38fd17ff9ea0</id>
<content type='text'>
Add support for Renesas R-Car Gen5 R8A78000 SoC into RT-VRAM
initialization driver. The changes are only a slight adjustment
to the register programming, therefore reuse the existing RT-VRAM
driver and parametrize those changes using driver data.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-rockchip-20260309' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next</title>
<updated>2026-03-10T16:07:04Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-03-10T14:17:13Z</published>
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<id>urn:sha1:d93a63acfe701aa07c9223ec454164c88e7eb43d</id>
<content type='text'>
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/29452

- New SoC support: RK3506, RK3582;
- New Board support: RK3528 FriendlyElec NanoPi Zero2;
- Other fixes
</content>
</entry>
<entry>
<title>ram: rockchip: Add basic support for RK3506</title>
<updated>2026-03-10T16:07:03Z</updated>
<author>
<name>Jonas Karlman</name>
<email>jonas@kwiboo.se</email>
</author>
<published>2026-01-31T23:38:15Z</published>
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<id>urn:sha1:05b8228648f27153a3cee025f9024aa9b1281ce0</id>
<content type='text'>
Add support for reading DRAM size information from PMUGRF os_reg2 reg.

Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Tested-by: Aaron Griffith &lt;aargri@gmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>treewide: Clean up DECLARE_GLOBAL_DATA_PTR usage</title>
<updated>2026-02-17T19:50:22Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2026-02-09T01:30:18Z</published>
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<id>urn:sha1:0f90b1e715f8abe41b0875752eb184f46032ff11</id>
<content type='text'>
Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.

Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.

Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt; #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal &lt;anshuld@ti.com&gt; #TI boards
Acked-by: Yao Zi &lt;me@ziyao.cc&gt; #TH1520
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>sunxi: extend R528/T113-s3/D1(s) DRAM initialisation</title>
<updated>2026-01-25T23:29:32Z</updated>
<author>
<name>Lukas Schmid</name>
<email>lukas.schmid@netcube.li</email>
</author>
<published>2025-10-26T11:41:17Z</published>
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<id>urn:sha1:d8ee42f113474c81f2d25a98e6cbcd60cf5bdfd5</id>
<content type='text'>
The T113-s4 SoC is using the same die as the T113-s3, but comes with
256MiB of co-packaged DRAM. Besides the doubled size, the DRAM chip
seems to be connected slightly differently, which requires to use a
different pin remapping.

Extend the DRAM initialisation code to add support for the T113-S4 aka
T113M4020DC0 by checking the SoC's CHIPID, which is stored in the first
word of the SID efuses.

Signed-off-by: Lukas Schmid &lt;lukas.schmid@netcube.li&gt;
Tested-by: John Watts &lt;contact@jookia.org&gt;
Reviewed-by: John Watts &lt;contact@jookia.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>kbuild: Bump the build system to 6.1</title>
<updated>2026-01-02T16:28:14Z</updated>
<author>
<name>Sughosh Ganu</name>
<email>sughosh.ganu@linaro.org</email>
</author>
<published>2025-12-16T09:16:24Z</published>
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<id>urn:sha1:bd3f9ee679b4d1456d0d3c261ab76788950e6096</id>
<content type='text'>
Our last sync with the kernel was 5.1.

We are so out of sync now, that tracking the patches and backporting
them one by one makes little sense and it's going to take ages.

This is an attempt to sync up Makefiles to 6.1.
Unfortunately due to sheer amount of patches this is not easy to review,
but that's what we decided during a community call for the bump to 5.1,
so we are following the same guidelines here.

Signed-off-by: Sughosh Ganu &lt;sughosh.ganu@linaro.org&gt;
Signed-off-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;a #rebased on -next
</content>
</entry>
<entry>
<title>ram: starfive: fix typo for unsupported DDR size</title>
<updated>2025-12-08T04:10:35Z</updated>
<author>
<name>E Shattow</name>
<email>e@freeshell.de</email>
</author>
<published>2025-10-30T06:23:34Z</published>
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<id>urn:sha1:87ecc2b6ca65dacb98a6b2747d329d33b72311c2</id>
<content type='text'>
Fix typo for "unsupport" size and improve description to Unknown DDR size.

Signed-off-by: E Shattow &lt;e@freeshell.de&gt;
Reviewed-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</content>
</entry>
<entry>
<title>ram: starfive: use SZ_8G for 8GB memory size</title>
<updated>2025-12-08T04:10:30Z</updated>
<author>
<name>E Shattow</name>
<email>e@freeshell.de</email>
</author>
<published>2025-10-30T06:23:33Z</published>
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<id>urn:sha1:e8874f361d6ce38b807d6c124dd51980c0475d46</id>
<content type='text'>
Replace numeric literal with SZ_8G consistent with other uses of types
from linux/types.h

Signed-off-by: E Shattow &lt;e@freeshell.de&gt;
Acked-by: Hal Feng &lt;hal.feng@starfivetech.com&gt;
Reviewed-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</content>
</entry>
<entry>
<title>ram: starfive: drop references to 16GB memory size</title>
<updated>2025-12-08T04:10:26Z</updated>
<author>
<name>E Shattow</name>
<email>e@freeshell.de</email>
</author>
<published>2025-10-30T06:23:32Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bccbe56710a53c37a98471fd483d1e44e5fb9b21'/>
<id>urn:sha1:bccbe56710a53c37a98471fd483d1e44e5fb9b21</id>
<content type='text'>
16GB memory size is not addressable on StarFive JH-7110 SoC because the
DRAM uncached alias begins at +8GB offset from start of DRAM. The logic
for 16GB memory size is a fall-through to the default for an unknown size.
Let's drop this unnecessary 16GB memory size and rely on the case default.

Signed-off-by: E Shattow &lt;e@freeshell.de&gt;
</content>
</entry>
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