Support i.MX8MP/N with start/stop/device_to_virt/is_running/load
implemented. The device static configuration is mostly reused from
Linux Kernel with adapation to U-Boot dm_rproc_ops.
The booting method:
- load mmc 2:2 0x90000000 /lib/firmware/imx8mp_m7_DDR_rpmsg_lite_str_echo_
rtos.elf
- rproc load 0 0x90000000 ${filesize}
- rproc start 0
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our Makefiles as part of the macros to determine when to do something in our Makefiles based on what phase of the build we are in. For consistency, bring this down to a single macro and use "$(PHASE_)" only. Signed-off-by: Tom Rini <trini@konsulko.com>
Greg Malysa <malysagreg@gmail.com> says: This series adds all of the supported peripheral drivers for the sc5xx series of SoCs from Analog Devices and other drivers that are used by the evaluation kits, such as a GPIO expander used by the EZLITE carrier boards. This series passes gitlab CI tests. Link: https://lore.kernel.org/r/20250226173150.13198-1-malysagreg@gmail.com
This adds the ability to load ldr-formatted files to the SHARC coprocessors using the rproc interface. Only a minimal subset of rproc functionality is supported: loading and starting the remote core. Secure boot and signed ldr verification are not available at this time through the U-Boot interface. Co-developed-by: Greg Malysa <malysagreg@gmail.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Co-developed-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Some K3 devices like AM64, AM62 devices have a M4 processor in MCU voltage domain. Add a remote proc driver to support this subsystem to be able to load and boot the M4 core. Signed-off-by: Hari Nagalla <hnagalla@ti.com> [Ryan: Fix implicitly include warning] Signed-off-by: Ryan Eatmon <reatmon@ti.com> [Judith: Cleanup driver, fix warnings, remove lreset logic] Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Andrew Davis <afd@ti.com>
Add R-Car Gen4 APMU controller remoteproc driver capable of starting the Cortex-R52 cores in Renesas R8A779G0 V4H/V4M SoC. The APMU IP is in fact a power management unit capable of additional operations, but those are not used by U-Boot so far. This requires slight adjustment to the SPL entry point code, as that is being executed on the Cortex-R52 #0 and the Cortex-R52 #0 enters an endless loop once it starts the rest of the SPL on Cortex-A76 core. The endless loop now checks for content of APMU CRBARP registers and tests whether valid VLD_BARP and BAREN_VALID bits are set, if so, the Cortex-R52 core exits the endless loop and jumps to address started in CRBARP[31:18] register in ARM mode, which is a trampoline code to jump to the final entry point. The trampoline code is in place to avoid limitation of CRBARP[31:18] address field, which limits the core start address to memory addresses aligned to 0x40000 or 256 kiB . The trampoline is placed at 0x40000 aligned address and jumps to the final entry point, which can be at an address with arbitrary alignment at instruction granularity. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is no-longer set. Signed-off-by: Simon Glass <sjg@chromium.org>
Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
The driver enables IPU support. Basically enables the clocks, timers, watchdog timers and bare minimal MMU and supports loading the firmware from mmc. Signed-off-by: Keerthy <j-keerthy@ti.com> [Amjad: fix compile warnings] Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
The K3 AM65x family of SoCs have the next generation of the PRU-ICSS processor subsystem, commonly referred to as ICSSG. Each ICSSG processor subsystem on AM65x SR1.0 contains two primary PRU cores and two new auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised ICSSG IP that is based off the subsequent IP revision used on J721E SoCs. This IP instance has two new custom auxiliary PRU cores called Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs. Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than a PRU), Control and debug feature sets, but is different in terms of sub-modules integrated around it and does not have the full capabilities associated with a PRU core. The RTU core is typically used to aid a PRU core in accelerating data transfers, while the Tx_PRU cores is normally used to control the TX L2 FIFO if enabled in Ethernet applications. Both can also be used to run independent applications. The RTU and Tx_PRU cores though share the same Data RAMs as the PRU cores, so the memories have to be partitioned carefully between different applications. The new cores also support a new sub-module called Task Manager to support two different context thread executions. The driver currently supports the AM65xx SoC Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210622063431.3151-3-lokeshvutla@ti.com