u-boot.git/drivers/reset/Kconfig, branch v2022.07Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/drivers/reset/Kconfig?h=v2022.072022-02-08T14:41:27Zreset: dra7: Add a reset driver2022-02-08T14:41:27ZKeerthyj-keerthy@ti.com2022-01-27T12:16:51Zurn:sha1:795b2c476f7dd7ecf9de95d8dca8ef0c8657dde4
Add a reset driver to bring IPs out of reset.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: reset_ops structure member "free" has been renamed to "rfree",
use the latter instead]
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
reset: zynqmp: Add reset controller for ZynqMP SoC2021-08-06T07:32:03ZMichal Simekmichal.simek@xilinx.com2021-07-30T06:00:10Zurn:sha1:3f123b74242bc076ba6cae6d45a11bd5da1d977f
Add firmware based reset controller for Xilinx ZynqMP SoC to let other
drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but
support for Xilinx Versal can be simply added. That's why reset_id and
nr_reset are assigned in probe folder.
Driver is inpired by driver from Linux kernel.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
board: sifive: add HiFive Unmatched board support2021-05-31T08:35:55ZGreen Wangreen.wan@sifive.com2021-05-27T13:52:13Zurn:sha1:70415e1e528db0856fedd4fa79b9f4a303a28c62
Add defconfig and board support for HiFive Unmatched.
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
drivers: clk: add fu740 support2021-05-31T08:35:54ZGreen Wangreen.wan@sifive.com2021-05-27T13:52:08Zurn:sha1:d56d79ed27c658f32f9a4bcae44e789b9c2879aa
Add fu740 support. One abstract layer is added for supporting
multiple chips such as fu540 and fu740.
Signed-off-by: Green Wan <green.wan@sifive.com>
riscv: sifive: Rename fu540 board to unleashed2021-04-08T07:37:29ZBin Mengbmeng.cn@gmail.com2021-03-17T03:10:58Zurn:sha1:ae2d9506a36ce2a31b2865c7071e3d20aa633340
In preparation to add SiFive Unmatched board support, let's rename
the existing fu540 board to unleashed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
reset: aspeed: Add AST2600 reset support2021-01-18T20:23:06ZChia-Wei, Wangchiawei_wang@aspeedtech.com2020-12-14T05:54:26Zurn:sha1:9fc21086b7fe7aa5ca328bb290c4cd78aeab6eaf
Add controller reset support through the
System Control Unit (SCU) of AST2600 SoC.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
cosmetic: reset: ast2500: Rename driver and configs2020-10-22T15:26:14ZChia-Wei, Wangchiawei_wang@aspeedtech.com2020-10-15T02:25:14Zurn:sha1:b2424cd2f4337cd36aa635d3bc52485f150d8ae6
1. Rename AST2500 reset driver from ast2500-reset.c
to reset-ast2500.c
2. Rename AST2500 reset kconfig option from AST2500_RESET
to RESET_AST2500
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
reset: ast2500: Use SCU for reset control2020-10-22T15:26:14ZChia-Wei, Wangchiawei_wang@aspeedtech.com2020-10-15T02:25:13Zurn:sha1:611a28ce271164941aac02feea19f1d87bd1cf32
The System Control Unit (SCU) controller of Aspeed
SoCs provides the reset control for each peripheral.
This patch refactors the reset method to leverage
the SCU reset control. Thus the driver dependency
on watchdog including dedicated WDT API and reset
flag encoding can be eliminated.
The Kconfig description is also updated accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
reset: add reset controller driver for SCMI agents2020-09-30T15:55:23ZEtienne Carriereetienne.carriere@linaro.org2020-09-09T16:44:06Zurn:sha1:34d76fefb2667d0ca138ff4fcf8bc8443032449f
This change introduces a reset controller driver for SCMI agent devices.
When SCMI agent and SCMI reset domain drivers are enabled, SCMI agent
binds a reset controller device for each SCMI reset domain protocol
devices enabled in the FDT.
SCMI reset driver is embedded upon CONFIG_RESET_SCMI=y. If enabled,
CONFIG_SCMI_AGENT is also enabled.
SCMI Reset Domain protocol is defined in the SCMI specification [1].
Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
reset: Add IPQ40xx reset controller driver2020-09-18T20:20:47ZRobert Markorobert.marko@sartura.hr2020-09-10T14:00:02Zurn:sha1:8ef7df5df39edbeb1367409cc340646810d2369b
On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets.
So since this will be needed by further drivers, lets add a driver for the reset controller.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>