<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/reset/Kconfig, branch v2023.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/reset/Kconfig?h=v2023.01</id>
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<updated>2022-08-26T14:55:45Z</updated>
<entry>
<title>reset: Convert ipq4019 driver to a generic Qcom driver</title>
<updated>2022-08-26T14:55:45Z</updated>
<author>
<name>Sumit Garg</name>
<email>sumit.garg@linaro.org</email>
</author>
<published>2022-08-04T14:27:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=42588276b3375f20cf372ff59c7d3712f55cf48f'/>
<id>urn:sha1:42588276b3375f20cf372ff59c7d3712f55cf48f</id>
<content type='text'>
Since the base functionality remains the same for a reset driver on Qcom
SoCs, so leverage that to convert ipq4019 specific reset driver to a
generic Qcom reset driver. With that one just need to provide SoC specific
reset table.

Signed-off-by: Sumit Garg &lt;sumit.garg@linaro.org&gt;
</content>
</entry>
<entry>
<title>reset: zynqmp: Add reset driver support for versal</title>
<updated>2022-07-26T06:27:15Z</updated>
<author>
<name>T Karthik Reddy</name>
<email>t.karthik.reddy@amd.com</email>
</author>
<published>2022-07-20T09:59:57Z</published>
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<id>urn:sha1:9df50817405b358c5dd8c669030de7b1f8b15cb8</id>
<content type='text'>
Add support for versal platform by adding "xlnx,versal-reset"
compatible string in zynqmp-reset driver. Reset numbering schema
for versal is not same as zynqmp, so nr_reset and reset_id are
set to zero. In case of assert/dessert, required device reset id
is sent from respective driver through struct reset_ctl.

Signed-off-by: T Karthik Reddy &lt;t.karthik.reddy@amd.com&gt;
Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@xilinx.com&gt;
Link: https://lore.kernel.org/r/20220720095959.29610-2-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>reset: dra7: Add a reset driver</title>
<updated>2022-02-08T14:41:27Z</updated>
<author>
<name>Keerthy</name>
<email>j-keerthy@ti.com</email>
</author>
<published>2022-01-27T12:16:51Z</published>
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<id>urn:sha1:795b2c476f7dd7ecf9de95d8dca8ef0c8657dde4</id>
<content type='text'>
Add a reset driver to bring IPs out of reset.

Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
[Amjad: reset_ops structure member "free" has been renamed to "rfree",
use the latter instead]
Signed-off-by: Amjad Ouled-Ameur &lt;aouledameur@baylibre.com&gt;
</content>
</entry>
<entry>
<title>reset: zynqmp: Add reset controller for ZynqMP SoC</title>
<updated>2021-08-06T07:32:03Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2021-07-30T06:00:10Z</published>
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<id>urn:sha1:3f123b74242bc076ba6cae6d45a11bd5da1d977f</id>
<content type='text'>
Add firmware based reset controller for Xilinx ZynqMP SoC to let other
drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but
support for Xilinx Versal can be simply added. That's why reset_id and
nr_reset are assigned in probe folder.
Driver is inpired by driver from Linux kernel.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>board: sifive: add HiFive Unmatched board support</title>
<updated>2021-05-31T08:35:55Z</updated>
<author>
<name>Green Wan</name>
<email>green.wan@sifive.com</email>
</author>
<published>2021-05-27T13:52:13Z</published>
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<id>urn:sha1:70415e1e528db0856fedd4fa79b9f4a303a28c62</id>
<content type='text'>
Add defconfig and board support for HiFive Unmatched.

Signed-off-by: Green Wan &lt;green.wan@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
</entry>
<entry>
<title>drivers: clk: add fu740 support</title>
<updated>2021-05-31T08:35:54Z</updated>
<author>
<name>Green Wan</name>
<email>green.wan@sifive.com</email>
</author>
<published>2021-05-27T13:52:08Z</published>
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<id>urn:sha1:d56d79ed27c658f32f9a4bcae44e789b9c2879aa</id>
<content type='text'>
Add fu740 support. One abstract layer is added for supporting
multiple chips such as fu540 and fu740.

Signed-off-by: Green Wan &lt;green.wan@sifive.com&gt;
</content>
</entry>
<entry>
<title>riscv: sifive: Rename fu540 board to unleashed</title>
<updated>2021-04-08T07:37:29Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-03-17T03:10:58Z</published>
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<id>urn:sha1:ae2d9506a36ce2a31b2865c7071e3d20aa633340</id>
<content type='text'>
In preparation to add SiFive Unmatched board support, let's rename
the existing fu540 board to unleashed.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>reset: aspeed: Add AST2600 reset support</title>
<updated>2021-01-18T20:23:06Z</updated>
<author>
<name>Chia-Wei, Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2020-12-14T05:54:26Z</published>
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<id>urn:sha1:9fc21086b7fe7aa5ca328bb290c4cd78aeab6eaf</id>
<content type='text'>
Add controller reset support through the
System Control Unit (SCU) of AST2600 SoC.

Signed-off-by: Chia-Wei, Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>cosmetic: reset: ast2500: Rename driver and configs</title>
<updated>2020-10-22T15:26:14Z</updated>
<author>
<name>Chia-Wei, Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2020-10-15T02:25:14Z</published>
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<id>urn:sha1:b2424cd2f4337cd36aa635d3bc52485f150d8ae6</id>
<content type='text'>
1. Rename AST2500 reset driver from ast2500-reset.c
   to reset-ast2500.c
2. Rename AST2500 reset kconfig option from AST2500_RESET
   to RESET_AST2500

Signed-off-by: Chia-Wei, Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>reset: ast2500: Use SCU for reset control</title>
<updated>2020-10-22T15:26:14Z</updated>
<author>
<name>Chia-Wei, Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2020-10-15T02:25:13Z</published>
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<id>urn:sha1:611a28ce271164941aac02feea19f1d87bd1cf32</id>
<content type='text'>
The System Control Unit (SCU) controller of Aspeed
SoCs provides the reset control for each peripheral.

This patch refactors the reset method to leverage
the SCU reset control. Thus the driver dependency
on watchdog including dedicated WDT API and reset
flag encoding can be eliminated.

The Kconfig description is also updated accordingly.

Signed-off-by: Chia-Wei, Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
</entry>
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