u-boot.git/drivers/reset/Kconfig, branch v2024.07

reset: npcm: Add support for Nuvoton NPCM BMC family

2024-01-16T22:05:29Z

Add reset controller driver for Nuvoton BMCs. The npcm reset driver not only supports reset each module reset but setting initial value of reset Control Registers. And The driver support each module reset. Signed-off-by: Jim Liu

clk/qcom: handle resets and clocks in one device

2024-01-16T12:26:23Z

Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly

reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC

2023-04-20T08:08:44Z

Add a DM reset driver for StarFive JH7110 SoC. Note that the register base address of reset controller is the same with the clock controller. Therefore, there is no device tree node alone for reset driver.It binds device node in the clock driver Signed-off-by: Yanhong Wang Tested-by: Conor Dooley

reset: at91: Add reset driver for basic assert/deassert operations

2023-01-05T08:06:35Z

Add support for at91 reset controller's basic assert/deassert operations. Since this driver conflicts with the SYSRESET driver because they both bind to the same RSTC node, implement a custom bind hook that would manually bind the sysreset driver, if enabled, to the same RSTC DT node. Furthermore, delete the no longer needed compatibles from the SYSRESET driver and rename it to make sure than any possible conflicts are avoided. Signed-off-by: Sergiu Moga Tested-by: Mihai Sain Reviewed-by: Claudiu Beznea

reset: Convert ipq4019 driver to a generic Qcom driver

2022-08-26T14:55:45Z

Since the base functionality remains the same for a reset driver on Qcom SoCs, so leverage that to convert ipq4019 specific reset driver to a generic Qcom reset driver. With that one just need to provide SoC specific reset table. Signed-off-by: Sumit Garg

reset: zynqmp: Add reset driver support for versal

2022-07-26T06:27:15Z

Add support for versal platform by adding "xlnx,versal-reset" compatible string in zynqmp-reset driver. Reset numbering schema for versal is not same as zynqmp, so nr_reset and reset_id are set to zero. In case of assert/dessert, required device reset id is sent from respective driver through struct reset_ctl. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20220720095959.29610-2-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek

reset: dra7: Add a reset driver

2022-02-08T14:41:27Z

Add a reset driver to bring IPs out of reset. Signed-off-by: Keerthy [Amjad: reset_ops structure member "free" has been renamed to "rfree", use the latter instead] Signed-off-by: Amjad Ouled-Ameur

reset: zynqmp: Add reset controller for ZynqMP SoC

2021-08-06T07:32:03Z

Add firmware based reset controller for Xilinx ZynqMP SoC to let other drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but support for Xilinx Versal can be simply added. That's why reset_id and nr_reset are assigned in probe folder. Driver is inpired by driver from Linux kernel. Signed-off-by: Michal Simek

board: sifive: add HiFive Unmatched board support

2021-05-31T08:35:55Z

Add defconfig and board support for HiFive Unmatched. Signed-off-by: Green Wan Reviewed-by: Bin Meng Reviewed-by: Rick Chen

drivers: clk: add fu740 support

2021-05-31T08:35:54Z

Add fu740 support. One abstract layer is added for supporting multiple chips such as fu540 and fu740. Signed-off-by: Green Wan