u-boot.git/drivers/reset/Kconfig, branch v2026.04

dm: core: Default to using DEVRES outside of xPL

2026-01-09T15:08:14Z

The devm alloc functions that we have may follow the Linux kernel model where allocations are (almost always) automatically free()'d. However, quite often we don't enable, in full U-Boot, the tracking and free()'ing functionality. This in turn leads to memory leaks because the driver author expects that since the functions have the same name as in the Linux Kernel they have the same behavior. In turn we then get functionally correct commits such as commit 00e1fed93c8c ("firmware: ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually add these calls. Rather than manually tracking allocations and implementing free()s, rework things so that we follow expectations by enabling the DEVRES functionality (outside of xPL phases). This turns DEVRES from a prompted symbol to a symbol that must be select'd, and we now remove our non-managed alloc/free functions from outside of xPL builds. Reviewed-by: Michael Trimarchi Signed-off-by: Tom Rini

reset: Tighten some reset driver dependencies

2025-08-14T16:59:09Z

A few reset drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini

reset: stm32mp25: add stm32mp25 reset driver

2025-06-11T07:42:55Z

Implement STM32MP25 reset drivers using stm32-core-reset API. This reset stm32-reset-core API and will be able to use DT binding index started from 0. This patch also moves legacy reset into stm32 directory reset. Signed-off-by: Gabriel Fernandez Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay Reviewed-by: Patrice Chotard

Merge patch series "airoha: Add initial support AN7581"

2025-04-01T14:45:46Z

Christian Marangi says: This little series adds initial support for Airoha AN7581 SoC. With the help of some backport patch, this use OF_UPSTREAM directly. Posting this to have the targer and the very basic driver. Ethernet, SNAND and eMMC support is already ready downstream and will be posted shortly after this gets approved. Having the first driver ready permits to separately push dedicate series for SNAND, eMMC and Ethrnet as they all depends on basic support of clock and reset and nothing else. Link: https://lore.kernel.org/r/20250314185941.27834-1-ansuelsmth@gmail.com

reset: airoha: Add driver for controlling reset line of AN7581

2025-04-01T14:44:51Z

Add driver for controlling the reset lines of AN7581. This is a detached version of the clock controller driver present in Linux only used to control reset lines. Driver gets loaded with the bind of the clock driver and doesn't require a compatible. This is needed as they share the same registers. Signed-off-by: Christian Marangi

riscv: reset: k1: Add reset driver

2025-03-25T08:31:40Z

Add spacemit reset driver. Signed-off-by: Huan Zhou Reviewed-by: Leo Yu-Chi Liang

reset: rzg2l-usbphy-ctrl: Connect up vbus regulator

2025-03-19T02:36:19Z

Bind the USB VBUS regulator driver under the USB PHY reset driver for the Renesas RZ/G2L and related SoCs. This additional bind is needed as the corresponding device tree node does not contain a compatible string. Reviewed-by: Marek Vasut Signed-off-by: Paul Barker

reset: rzg2l-usbphy-ctrl: Add new driver

2025-03-19T02:36:19Z

Add a new driver to control the USB 2.0 PHY reset controller on the Renesas RZ/G2L and related SoCs. Signed-off-by: Paul Barker Reviewed-by: Marek Vasut

reset: npcm: Add support for Nuvoton NPCM BMC family

2024-01-16T22:05:29Z

Add reset controller driver for Nuvoton BMCs. The npcm reset driver not only supports reset each module reset but setting initial value of reset Control Registers. And The driver support each module reset. Signed-off-by: Jim Liu

clk/qcom: handle resets and clocks in one device

2024-01-16T12:26:23Z

Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly