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<title>u-boot.git/drivers/reset/Makefile, branch v2022.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>reset: zynqmp: Add reset controller for ZynqMP SoC</title>
<updated>2021-08-06T07:32:03+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2021-07-30T06:00:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3f123b74242bc076ba6cae6d45a11bd5da1d977f'/>
<id>3f123b74242bc076ba6cae6d45a11bd5da1d977f</id>
<content type='text'>
Add firmware based reset controller for Xilinx ZynqMP SoC to let other
drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but
support for Xilinx Versal can be simply added. That's why reset_id and
nr_reset are assigned in probe folder.
Driver is inpired by driver from Linux kernel.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
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<pre>
Add firmware based reset controller for Xilinx ZynqMP SoC to let other
drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but
support for Xilinx Versal can be simply added. That's why reset_id and
nr_reset are assigned in probe folder.
Driver is inpired by driver from Linux kernel.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>reset: aspeed: Add AST2600 reset support</title>
<updated>2021-01-18T20:23:06+00:00</updated>
<author>
<name>Chia-Wei, Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2020-12-14T05:54:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9fc21086b7fe7aa5ca328bb290c4cd78aeab6eaf'/>
<id>9fc21086b7fe7aa5ca328bb290c4cd78aeab6eaf</id>
<content type='text'>
Add controller reset support through the
System Control Unit (SCU) of AST2600 SoC.

Signed-off-by: Chia-Wei, Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
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<pre>
Add controller reset support through the
System Control Unit (SCU) of AST2600 SoC.

Signed-off-by: Chia-Wei, Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cosmetic: reset: ast2500: Rename driver and configs</title>
<updated>2020-10-22T15:26:14+00:00</updated>
<author>
<name>Chia-Wei, Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2020-10-15T02:25:14+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b2424cd2f4337cd36aa635d3bc52485f150d8ae6'/>
<id>b2424cd2f4337cd36aa635d3bc52485f150d8ae6</id>
<content type='text'>
1. Rename AST2500 reset driver from ast2500-reset.c
   to reset-ast2500.c
2. Rename AST2500 reset kconfig option from AST2500_RESET
   to RESET_AST2500

Signed-off-by: Chia-Wei, Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</content>
<content type='xhtml'>
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<pre>
1. Rename AST2500 reset driver from ast2500-reset.c
   to reset-ast2500.c
2. Rename AST2500 reset kconfig option from AST2500_RESET
   to RESET_AST2500

Signed-off-by: Chia-Wei, Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>reset: add reset controller driver for SCMI agents</title>
<updated>2020-09-30T15:55:23+00:00</updated>
<author>
<name>Etienne Carriere</name>
<email>etienne.carriere@linaro.org</email>
</author>
<published>2020-09-09T16:44:06+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=34d76fefb2667d0ca138ff4fcf8bc8443032449f'/>
<id>34d76fefb2667d0ca138ff4fcf8bc8443032449f</id>
<content type='text'>
This change introduces a reset controller driver for SCMI agent devices.
When SCMI agent and SCMI reset domain drivers are enabled, SCMI agent
binds a reset controller device for each SCMI reset domain protocol
devices enabled in the FDT.

SCMI reset driver is embedded upon CONFIG_RESET_SCMI=y. If enabled,
CONFIG_SCMI_AGENT is also enabled.

SCMI Reset Domain protocol is defined in the SCMI specification [1].

Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi
Signed-off-by: Etienne Carriere &lt;etienne.carriere@linaro.org&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This change introduces a reset controller driver for SCMI agent devices.
When SCMI agent and SCMI reset domain drivers are enabled, SCMI agent
binds a reset controller device for each SCMI reset domain protocol
devices enabled in the FDT.

SCMI reset driver is embedded upon CONFIG_RESET_SCMI=y. If enabled,
CONFIG_SCMI_AGENT is also enabled.

SCMI Reset Domain protocol is defined in the SCMI specification [1].

Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi
Signed-off-by: Etienne Carriere &lt;etienne.carriere@linaro.org&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>reset: Add IPQ40xx reset controller driver</title>
<updated>2020-09-18T20:20:47+00:00</updated>
<author>
<name>Robert Marko</name>
<email>robert.marko@sartura.hr</email>
</author>
<published>2020-09-10T14:00:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8ef7df5df39edbeb1367409cc340646810d2369b'/>
<id>8ef7df5df39edbeb1367409cc340646810d2369b</id>
<content type='text'>
On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets.
So since this will be needed by further drivers, lets add a driver for the reset controller.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
</content>
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<pre>
On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets.
So since this will be needed by further drivers, lets add a driver for the reset controller.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>configs: reset: fu540: enable dm reset framework for SiFive</title>
<updated>2020-08-04T01:19:41+00:00</updated>
<author>
<name>Sagar Shrikant Kadam</name>
<email>sagar.kadam@sifive.com</email>
</author>
<published>2020-07-29T09:36:14+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ed50d3fae49b9dad58674b6609913beeac824e42'/>
<id>ed50d3fae49b9dad58674b6609913beeac824e42</id>
<content type='text'>
Add necessary defconfig and Kconfig entries to enable SiFive SoC's
reset driver so as to utilise U-Boot's reset framework.

Signed-off-by: Sagar Shrikant Kadam &lt;sagar.kadam@sifive.com&gt;
Reviewed-by: Pragnesh Patel &lt;Pragnesh.patel@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Tested-by: Bin Meng &lt;bin.meng@windriver.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add necessary defconfig and Kconfig entries to enable SiFive SoC's
reset driver so as to utilise U-Boot's reset framework.

Signed-off-by: Sagar Shrikant Kadam &lt;sagar.kadam@sifive.com&gt;
Reviewed-by: Pragnesh Patel &lt;Pragnesh.patel@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Tested-by: Bin Meng &lt;bin.meng@windriver.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>reset: Add Raspberry Pi 4 firmware reset controller</title>
<updated>2020-07-10T09:49:28+00:00</updated>
<author>
<name>Nicolas Saenz Julienne</name>
<email>nsaenzjulienne@suse.de</email>
</author>
<published>2020-06-29T16:37:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f676eb217bdff3bd734a42c8f9bbc58c9100055c'/>
<id>f676eb217bdff3bd734a42c8f9bbc58c9100055c</id>
<content type='text'>
Raspberry Pi 4's co-processor controls some of the board's HW
initialization process, but it's up to Linux to trigger it when
relevant. Introduce a reset controller capable of interfacing with
RPi4's co-processor that models these firmware initialization routines as
reset lines.

Signed-off-by: Nicolas Saenz Julienne &lt;nsaenzjulienne@suse.de&gt;
Signed-off-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
</content>
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<pre>
Raspberry Pi 4's co-processor controls some of the board's HW
initialization process, but it's up to Linux to trigger it when
relevant. Introduce a reset controller capable of interfacing with
RPi4's co-processor that models these firmware initialization routines as
reset lines.

Signed-off-by: Nicolas Saenz Julienne &lt;nsaenzjulienne@suse.de&gt;
Signed-off-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>reset: Add generic reset driver</title>
<updated>2020-07-01T07:01:21+00:00</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2020-06-24T10:41:14+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=038b13ee8134ba755a323732f3b2b838b9dc17a4'/>
<id>038b13ee8134ba755a323732f3b2b838b9dc17a4</id>
<content type='text'>
This patch adds a generic reset driver. It is designed to be useful when
one has a register in a regmap which contains bits that reset other
devices. I thought this seemed like a very generic use, so here is a
generic driver. The overall structure has been modeled on the syscon-reboot
driver.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds a generic reset driver. It is designed to be useful when
one has a register in a regmap which contains bits that reset other
devices. I thought this seemed like a very generic use, so here is a
generic driver. The overall structure has been modeled on the syscon-reboot
driver.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARC: HSDK: introduce reset driver</title>
<updated>2019-11-01T13:45:40+00:00</updated>
<author>
<name>Eugeniy Paltsev</name>
<email>Eugeniy.Paltsev@synopsys.com</email>
</author>
<published>2019-10-08T16:29:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c597e248d9794ab40f68586bfa9e3596949df44b'/>
<id>c597e248d9794ab40f68586bfa9e3596949df44b</id>
<content type='text'>
Introduce reset driver for Synopsys ARC HSDK SoC

Signed-off-by: Eugeniy Paltsev &lt;Eugeniy.Paltsev@synopsys.com&gt;
Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
<content type='xhtml'>
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<pre>
Introduce reset driver for Synopsys ARC HSDK SoC

Signed-off-by: Eugeniy Paltsev &lt;Eugeniy.Paltsev@synopsys.com&gt;
Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>reset: add reset controller driver for MediaTek MIPS platform</title>
<updated>2019-10-25T15:20:44+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2019-09-25T09:45:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f7ae6b682c42a82a38ebeb3ea4a20f23ca623563'/>
<id>f7ae6b682c42a82a38ebeb3ea4a20f23ca623563</id>
<content type='text'>
This patch adds reset controller driver for MediaTek MIPS platform and
header file for mt7628.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds reset controller driver for MediaTek MIPS platform and
header file for mt7628.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
