u-boot.git/drivers/reset, branch next

reset: spacemit: k1: drop legacy spacemit,k1-reset driver

2026-07-21T08:31:10Z

After the K1 build switched to dts/upstream/src/riscv/spacemit/ and the local arch/riscv/dts/k1.dtsi was deleted, the legacy reset-controller@d4050000 DT node no longer exists. The of_match driver in drivers/reset/reset-spacemit-k1.c (compatible "spacemit,k1-reset") matches nothing and only sits in the binary as dead code. Remove the legacy driver file, its Makefile entry, the RESET_SPACEMIT_K1 Kconfig symbol, and its bananapi-f3_defconfig selection. The new syscon-bound reset driver under drivers/reset/spacemit/ has no DT of_match of its own and is spawned by the K1 clock drivers, so gate the subdirectory on CONFIG_CLK_SPACEMIT_K1 instead. Signed-off-by: Guodong Xu

reset: spacemit: k1: introduce syscon-bound reset driver

2026-07-21T08:31:10Z

The existing K1 reset driver (drivers/reset/reset-spacemit-k1.c) binds via DT of_match against a top-level reset-controller node, but kernel mainline DT for K1 has no such node: the mpmu, apbc, apmu and apbc2 syscons each spawn their own reset device as an auxiliary of the clock controller. The legacy driver therefore cannot consume it. Add a new reset driver at drivers/reset/spacemit/reset-spacemit-k1.c bound by name from each per-syscon clock driver via device_bind_driver_to_node(), without DT of_match, mirroring the kernel's auxiliary-device pattern. To keep the series bisectable, this driver coexists link-cleanly with the legacy spacemit,k1-reset driver during the transition. A follow-up patch that switches the K1 build to dts/upstream/src/riscv/spacemit/ will drop the legacy driver. Signed-off-by: Guodong Xu

Merge patch series "arm: aspeed: add initial AST2700 SoC support"

2026-06-29T21:29:56Z

Ryan Chen says: AST2700 is the 8th generation of Integrated Remote Management Processor introduced by ASPEED Technology Inc. It is a Board Management Controller (BMC) SoC family with a dual-die architecture: SoC0 ("CPU" die with four ARM Cortex-A35 application cores) and SoC1 ("IO" die with peripherals) each SoC have its own SCU PLLs, clock dividers and reset domains. Link: https://lore.kernel.org/r/20260612-ast2700_clk-v4-0-9bea29cfdc39@aspeedtech.com

reset: ast2700: add reset driver support

2026-06-29T19:43:20Z

Add reset controller driver for the dual-die AST2700 SoC. The controller manages module-level reset signals via the modrst register block at offset 0x200 within each SCU. Signed-off-by: Ryan Chen

Merge tag 'v2026.07-rc5' into next

2026-06-22T22:42:41Z

Prepare v2026.07-rc5

Merge assorted patches to use device API to replace devfdt_ helpers

2026-06-09T22:00:11Z

These assorted patch series from Peng Fan (OSS) have the goal to remove the direct usage of devfdt_ APIs in drivers. The device APIs supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers.

reset: ast: Use dev_read_addr_ptr()

2026-06-09T20:53:34Z

Use dev_read_addr_ptr() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. While at here, correct error return value, when priv->scu is NULL, PTR_ERR(priv->scu) is 0 which implies success. Change to return '-EINVAL'. No functional changes. Signed-off-by: Peng Fan

Merge tag 'v2026.07-rc4' into next

2026-06-08T21:28:18Z

Prepare v2026.07-rc4

reset: rockchip: make device resets available in SPL

2026-06-08T13:32:40Z

Enable the Rockchip reset controller driver in SPL to allow resetting attached devices like UFS during early boot. Reviewed-by: Jonas Karlman Signed-off-by: Alexey Charkov

reset: zynqmp: Implement rst_reset using PM_RESET_ACTION_PULSE

2026-06-08T08:50:06Z

Implement the rst_reset operation in the ZynqMP reset driver to use PM_RESET_ACTION_PULSE. This allows the reset controller to perform a reset pulse in a single firmware call instead of separate assert and deassert calls. This matches the Linux kernel implementation of zynqmp_reset_reset(). Reviewed-by: Simon Glass Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/be77d6f1b60f591ef626c14229d85c5cab867967.1779709539.git.michal.simek@amd.com