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<title>u-boot.git/drivers/reset, branch v2022.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>clk: sunxi: Move header out of arch directory</title>
<updated>2021-10-11T09:46:44+00:00</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-09-12T16:48:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=21d314a6612564ee202d8a8189ed37d5c6abf0dd'/>
<id>21d314a6612564ee202d8a8189ed37d5c6abf0dd</id>
<content type='text'>
The CCU header is only used by the DM drivers, not any platform code.
Its current location adds an artificial dependency on CONFIG_ARM and
ARCH_SUNXI, which will be problematic when adding the CCU driver for
a RISC-V sunxi platform.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
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<pre>
The CCU header is only used by the DM drivers, not any platform code.
Its current location adds an artificial dependency on CONFIG_ARM and
ARCH_SUNXI, which will be problematic when adding the CCU driver for
a RISC-V sunxi platform.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>WS cleanup: remove trailing white space</title>
<updated>2021-09-30T12:08:56+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2021-09-27T15:42:38+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0a50b3c97b3408e52589d873d4c7b54ad365a76c'/>
<id>0a50b3c97b3408e52589d873d4c7b54ad365a76c</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>WS cleanup: remove trailing empty lines</title>
<updated>2021-09-30T12:08:56+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2021-09-27T15:42:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=66356b4c06c934021f6cb58d93877427162b369f'/>
<id>66356b4c06c934021f6cb58d93877427162b369f</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
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<pre>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>reset: zynqmp: Add reset controller for ZynqMP SoC</title>
<updated>2021-08-06T07:32:03+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2021-07-30T06:00:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3f123b74242bc076ba6cae6d45a11bd5da1d977f'/>
<id>3f123b74242bc076ba6cae6d45a11bd5da1d977f</id>
<content type='text'>
Add firmware based reset controller for Xilinx ZynqMP SoC to let other
drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but
support for Xilinx Versal can be simply added. That's why reset_id and
nr_reset are assigned in probe folder.
Driver is inpired by driver from Linux kernel.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
<content type='xhtml'>
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<pre>
Add firmware based reset controller for Xilinx ZynqMP SoC to let other
drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but
support for Xilinx Versal can be simply added. That's why reset_id and
nr_reset are assigned in probe folder.
Driver is inpired by driver from Linux kernel.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>reset: ast2600: Fix missing reference operator</title>
<updated>2021-07-24T12:57:53+00:00</updated>
<author>
<name>Chia-Wei Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2021-07-20T07:01:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bc7b38450baa4efe71bb14ea8aab9e8d206073fd'/>
<id>bc7b38450baa4efe71bb14ea8aab9e8d206073fd</id>
<content type='text'>
Fix missing reference operator '&amp;' to correctly get
HW register addresses for writel().

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
</content>
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<pre>
Fix missing reference operator '&amp;' to correctly get
HW register addresses for writel().

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>reset: Avoid a warning in devm_reset_bulk_get_by_node()</title>
<updated>2021-07-15T22:42:05+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-05-14T01:39:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ca4c24509c60cfc95563d25b482cfed3789aca59'/>
<id>ca4c24509c60cfc95563d25b482cfed3789aca59</id>
<content type='text'>
The devres_alloc() function is intended to avoid the need for freeing
memory, although in practice it may not be enabled, thus leading to a true
leak.

Nevertheless this is intended. Add a comment to explain this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reported-by: Coverity (CID: 312952)
</content>
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<pre>
The devres_alloc() function is intended to avoid the need for freeing
memory, although in practice it may not be enabled, thus leading to a true
leak.

Nevertheless this is intended. Add a comment to explain this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reported-by: Coverity (CID: 312952)
</pre>
</div>
</content>
</entry>
<entry>
<title>reset: uniphier: Add PCIe reset entry</title>
<updated>2021-07-14T20:48:06+00:00</updated>
<author>
<name>Kunihiko Hayashi</name>
<email>hayashi.kunihiko@socionext.com</email>
</author>
<published>2021-07-06T10:01:07+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=34707b32edad37427327a5358433d0591a07dcc1'/>
<id>34707b32edad37427327a5358433d0591a07dcc1</id>
<content type='text'>
Add reset control for PCIe controller on each SoC.

Signed-off-by: Kunihiko Hayashi &lt;hayashi.kunihiko@socionext.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add reset control for PCIe controller on each SoC.

Signed-off-by: Kunihiko Hayashi &lt;hayashi.kunihiko@socionext.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: define LOG_CATEGORY for all uclass</title>
<updated>2021-07-06T16:38:03+00:00</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@foss.st.com</email>
</author>
<published>2021-04-27T09:02:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b953ec2bca1ebe059366e870eb4bec5e7af9c36b'/>
<id>b953ec2bca1ebe059366e870eb4bec5e7af9c36b</id>
<content type='text'>
Define LOG_CATEGORY for all uclass to allow filtering with
log command.

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
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<pre>
Define LOG_CATEGORY for all uclass to allow filtering with
log command.

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>board: sifive: add HiFive Unmatched board support</title>
<updated>2021-05-31T08:35:55+00:00</updated>
<author>
<name>Green Wan</name>
<email>green.wan@sifive.com</email>
</author>
<published>2021-05-27T13:52:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=70415e1e528db0856fedd4fa79b9f4a303a28c62'/>
<id>70415e1e528db0856fedd4fa79b9f4a303a28c62</id>
<content type='text'>
Add defconfig and board support for HiFive Unmatched.

Signed-off-by: Green Wan &lt;green.wan@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
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<pre>
Add defconfig and board support for HiFive Unmatched.

Signed-off-by: Green Wan &lt;green.wan@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: clk: add fu740 support</title>
<updated>2021-05-31T08:35:54+00:00</updated>
<author>
<name>Green Wan</name>
<email>green.wan@sifive.com</email>
</author>
<published>2021-05-27T13:52:08+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d56d79ed27c658f32f9a4bcae44e789b9c2879aa'/>
<id>d56d79ed27c658f32f9a4bcae44e789b9c2879aa</id>
<content type='text'>
Add fu740 support. One abstract layer is added for supporting
multiple chips such as fu540 and fu740.

Signed-off-by: Green Wan &lt;green.wan@sifive.com&gt;
</content>
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<pre>
Add fu740 support. One abstract layer is added for supporting
multiple chips such as fu540 and fu740.

Signed-off-by: Green Wan &lt;green.wan@sifive.com&gt;
</pre>
</div>
</content>
</entry>
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