u-boot.git/drivers/reset, branch v2023.07 Unnamed repository; edit this file 'description' to name the repository. reset: rockchip: implement rk3588 lookup table 2023-05-17T09:36:18+00:00 Eugen Hristev eugen.hristev@collabora.com 2023-05-15T10:55:04+00:00 bb52f1c604d09b0c378addfa5c75c82efc219b03 The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> 
The current DT bindings for the rk3588 clock use a different ID than the
one that is supposed to be written to the hardware registers.
Thus, we cannot use directly the id provided in the phandle, but rather
use a lookup table to correctly setup the hardware.

This approach has been implemented already in Linux, by commit :
f1c506d152ff ("clk: rockchip: add clock controller for the RK3588")

Hence, implement a similar approach using the lookup table, and adapt
the existing reset driver to work with SoCs using lookup table.
The file rst-rk3588.c has been copied as much as possible from Linux.

Adapt the clk rk3588 driver as well to bind the reset driver with the
lookup table.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
reset: reset-rockchip: fix trivial line spacing alignment 2023-05-09T10:56:16+00:00 Eugen Hristev eugen.hristev@collabora.com 2023-04-11T07:20:40+00:00 4a08ca61926dc91cd709f3992c22a5ab84dc096e Fix line spacing aligment in bind function Fixes: 760188c1aa5b ("rockchip: reset: support a (common) rockchip reset drivers") Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
Fix line spacing aligment in bind function

Fixes: 760188c1aa5b ("rockchip: reset: support a (common) rockchip reset drivers")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC 2023-04-20T08:08:44+00:00 Yanhong Wang yanhong.wang@starfivetech.com 2023-03-29T03:42:11+00:00 d13de4faafbdb675515c57dcadf4a78205767ace Add a DM reset driver for StarFive JH7110 SoC. Note that the register base address of reset controller is the same with the clock controller. Therefore, there is no device tree node alone for reset driver.It binds device node in the clock driver Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> 
Add a DM reset driver for StarFive JH7110 SoC.

Note that the register base address of reset controller is the
same with the clock controller. Therefore, there is no device
tree node alone for reset driver.It binds device node in
the clock driver

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
reset: uniphier: Add USB glue reset support 2023-02-22T18:40:11+00:00 Kunihiko Hayashi hayashi.kunihiko@socionext.com 2023-02-20T05:50:30+00:00 1c866de57bfcd2250fba09f5c186a4c3c256e31a Add reset control support in USB glue logic. This needs to control the external clocks and resets for the logic before accessing the glue logic. The USB dm tree when using dwc3-generic is the following: USB glue +-- controller (need controller-reset) +-- controller-reset (need syscon-reset) +-- phy The controller needs to deassert "controller-reset" in USB glue before the controller registers are accessed. The glue needs to deassert "syscon-reset" before the glue registers are accessed. The glue itself doesn't have "syscon-reset", so the controller-reset controls "syscon-reset" instead. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de> 
Add reset control support in USB glue logic. This needs to control
the external clocks and resets for the logic before accessing the
glue logic.

The USB dm tree when using dwc3-generic is the following:

   USB glue
     +-- controller       (need controller-reset)
     +-- controller-reset (need syscon-reset)
     +-- phy

The controller needs to deassert "controller-reset" in USB glue before
the controller registers are accessed. The glue needs to deassert
"syscon-reset" before the glue registers are accessed.

The glue itself doesn't have "syscon-reset", so the controller-reset
controls "syscon-reset" instead.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
reset: Allow reset_get_by_name() with NULL name 2023-02-12T18:44:20+00:00 Samuel Holland samuel@sholland.org 2023-01-22T00:02:52+00:00 5a675abfe7c3f12b475cc0a6c9074a9fbe0b6bb6 This allows devm_reset_control_get(dev, NULL) to work and get the first reset control, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230122000252.53642-2-samuel@sholland.org 
This allows devm_reset_control_get(dev, NULL) to work and get the first
reset control, which is common in code ported from Linux.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230122000252.53642-2-samuel@sholland.org
reset: at91: Add reset driver for basic assert/deassert operations 2023-01-05T08:06:35+00:00 Sergiu Moga sergiu.moga@microchip.com 2023-01-04T14:03:18+00:00 61040097a9d1c8022bae7936c52b729ff1adb163 Add support for at91 reset controller's basic assert/deassert operations. Since this driver conflicts with the SYSRESET driver because they both bind to the same RSTC node, implement a custom bind hook that would manually bind the sysreset driver, if enabled, to the same RSTC DT node. Furthermore, delete the no longer needed compatibles from the SYSRESET driver and rename it to make sure than any possible conflicts are avoided. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Tested-by: Mihai Sain <mihai.sain@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> 
Add support for at91 reset controller's basic assert/deassert
operations. Since this driver conflicts with the
SYSRESET driver because they both bind to the same RSTC node,
implement a custom bind hook that would manually bind the
sysreset driver, if enabled, to the same RSTC DT node.
Furthermore, delete the no longer needed compatibles from the
SYSRESET driver and rename it to make sure than any possible
conflicts are avoided.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Tested-by: Mihai Sain <mihai.sain@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
reset: zynqmp: Enable reset driver for Versal NET 2022-09-26T12:23:29+00:00 Jay Buddhabhatti jay.buddhabhatti@amd.com 2022-09-19T12:21:08+00:00 a41c33992a89de2bcae0e361d70818def70b1783 Enable zynqmp reset driver for Versal NET. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c8c26618f87d8451c6ffa9487809a24718bff6a7.1663589964.git.michal.simek@amd.com 
Enable zynqmp reset driver for Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8c26618f87d8451c6ffa9487809a24718bff6a7.1663589964.git.michal.simek@amd.com
reset: qcom: Add support for QCS404 SoC reset table 2022-08-26T14:55:45+00:00 Sumit Garg sumit.garg@linaro.org 2022-08-04T14:27:12+00:00 9b6f90ca9251e9a2c366fb676b7f49f42287b8c7 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> 
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
reset: Convert ipq4019 driver to a generic Qcom driver 2022-08-26T14:55:45+00:00 Sumit Garg sumit.garg@linaro.org 2022-08-04T14:27:11+00:00 42588276b3375f20cf372ff59c7d3712f55cf48f Since the base functionality remains the same for a reset driver on Qcom SoCs, so leverage that to convert ipq4019 specific reset driver to a generic Qcom reset driver. With that one just need to provide SoC specific reset table. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> 
Since the base functionality remains the same for a reset driver on Qcom
SoCs, so leverage that to convert ipq4019 specific reset driver to a
generic Qcom reset driver. With that one just need to provide SoC specific
reset table.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
reset: zynqmp: Add reset driver support for versal 2022-07-26T06:27:15+00:00 T Karthik Reddy t.karthik.reddy@amd.com 2022-07-20T09:59:57+00:00 9df50817405b358c5dd8c669030de7b1f8b15cb8 Add support for versal platform by adding "xlnx,versal-reset" compatible string in zynqmp-reset driver. Reset numbering schema for versal is not same as zynqmp, so nr_reset and reset_id are set to zero. In case of assert/dessert, required device reset id is sent from respective driver through struct reset_ctl. Signed-off-by: T Karthik Reddy <t.karthik.reddy@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220720095959.29610-2-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com> 
Add support for versal platform by adding "xlnx,versal-reset"
compatible string in zynqmp-reset driver. Reset numbering schema
for versal is not same as zynqmp, so nr_reset and reset_id are
set to zero. In case of assert/dessert, required device reset id
is sent from respective driver through struct reset_ctl.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220720095959.29610-2-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>