u-boot.git/drivers/reset, branch v2023.07-rc2

reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC

2023-04-20T08:08:44Z

Add a DM reset driver for StarFive JH7110 SoC. Note that the register base address of reset controller is the same with the clock controller. Therefore, there is no device tree node alone for reset driver.It binds device node in the clock driver Signed-off-by: Yanhong Wang Tested-by: Conor Dooley

reset: uniphier: Add USB glue reset support

2023-02-22T18:40:11Z

Add reset control support in USB glue logic. This needs to control the external clocks and resets for the logic before accessing the glue logic. The USB dm tree when using dwc3-generic is the following: USB glue +-- controller (need controller-reset) +-- controller-reset (need syscon-reset) +-- phy The controller needs to deassert "controller-reset" in USB glue before the controller registers are accessed. The glue needs to deassert "syscon-reset" before the glue registers are accessed. The glue itself doesn't have "syscon-reset", so the controller-reset controls "syscon-reset" instead. Signed-off-by: Kunihiko Hayashi Reviewed-by: Marek Vasut

reset: Allow reset_get_by_name() with NULL name

2023-02-12T18:44:20Z

This allows devm_reset_control_get(dev, NULL) to work and get the first reset control, which is common in code ported from Linux. Signed-off-by: Samuel Holland Reviewed-by: Simon Glass Link: https://lore.kernel.org/r/20230122000252.53642-2-samuel@sholland.org

reset: at91: Add reset driver for basic assert/deassert operations

2023-01-05T08:06:35Z

Add support for at91 reset controller's basic assert/deassert operations. Since this driver conflicts with the SYSRESET driver because they both bind to the same RSTC node, implement a custom bind hook that would manually bind the sysreset driver, if enabled, to the same RSTC DT node. Furthermore, delete the no longer needed compatibles from the SYSRESET driver and rename it to make sure than any possible conflicts are avoided. Signed-off-by: Sergiu Moga Tested-by: Mihai Sain Reviewed-by: Claudiu Beznea

reset: zynqmp: Enable reset driver for Versal NET

2022-09-26T12:23:29Z

Enable zynqmp reset driver for Versal NET. Signed-off-by: Jay Buddhabhatti Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c8c26618f87d8451c6ffa9487809a24718bff6a7.1663589964.git.michal.simek@amd.com

reset: qcom: Add support for QCS404 SoC reset table

2022-08-26T14:55:45Z

Signed-off-by: Sumit Garg

reset: Convert ipq4019 driver to a generic Qcom driver

2022-08-26T14:55:45Z

Since the base functionality remains the same for a reset driver on Qcom SoCs, so leverage that to convert ipq4019 specific reset driver to a generic Qcom reset driver. With that one just need to provide SoC specific reset table. Signed-off-by: Sumit Garg

reset: zynqmp: Add reset driver support for versal

2022-07-26T06:27:15Z

Add support for versal platform by adding "xlnx,versal-reset" compatible string in zynqmp-reset driver. Reset numbering schema for versal is not same as zynqmp, so nr_reset and reset_id are set to zero. In case of assert/dessert, required device reset id is sent from respective driver through struct reset_ctl. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20220720095959.29610-2-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek

reset: sunxi: Reuse the platform data from the clock driver

2022-07-18T08:37:50Z

The clock and reset drivers use the exact same platform data. Simplify them by sharing the object. This is safe because the parent device (the clock device) always gets its driver model callbacks run first. Signed-off-by: Samuel Holland Acked-by: Andre Przywara Signed-off-by: Andre Przywara

reset: sunxi: Convert driver private data to platform data

2022-07-18T08:37:50Z

The reason here is the same as the reason for changing the clock driver: platform data can be provided when binding the driver. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara