u-boot.git/drivers/rng/Makefile, branch master Unnamed repository; edit this file 'description' to name the repository. global: Rename SPL_TPL_ to PHASE_ 2024-10-11T17:44:48+00:00 Simon Glass sjg@chromium.org 2024-09-30T01:49:54+00:00 5c10c8badf8233cac1593cd2bef4d0379ac9e5bd Use PHASE_ as the symbol to select a particular XPL build. This means that SPL_TPL_ is no-longer set. Update the comment in bootstage to refer to this symbol, instead of SPL_ Signed-off-by: Simon Glass <sjg@chromium.org> 
Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.

Update the comment in bootstage to refer to this symbol, instead of
SPL_

Signed-off-by: Simon Glass <sjg@chromium.org>
rng: Add Exynos TRNG driver 2024-07-24T07:37:09+00:00 Sam Protsenko semen.protsenko@linaro.org 2024-07-23T18:14:38+00:00 9344efc9bb7a28a1aca395d2762ca2d5dc128405 Add True Random Number Generator (TRNG) driver for Exynos chips. This implementation is heavily based on Linux kernel's counterpart [1]. It also follows upstream dt-bindings [2]. TRNG block is usually a part of SSS (Security Sub System) IP-core on Exynos chips. Because SSS access on Exynos850 is protected by TZPC (TrustZone Protection Control), it's not possible to read/write TRNG registers from U-Boot, as it's running in EL1 mode. Instead, the corresponding SMC calls should be used to make the secure software running in EL3 mode access it for us. Those SMC calls are handled by LDFW (Loadable Firmware), which has to be loaded first. For example, for E850-96 board it's done in its board_init(), so by the time RNG capabilities are needed the LDFW should be already loaded and TRNG should be functional. [1] drivers/char/hw_random/exynos-trng.c [2] dts/upstream/Bindings/rng/samsung,exynos5250-trng.yaml Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> 
Add True Random Number Generator (TRNG) driver for Exynos chips. This
implementation is heavily based on Linux kernel's counterpart [1]. It
also follows upstream dt-bindings [2].

TRNG block is usually a part of SSS (Security Sub System) IP-core on
Exynos chips. Because SSS access on Exynos850 is protected by TZPC
(TrustZone Protection Control), it's not possible to read/write TRNG
registers from U-Boot, as it's running in EL1 mode. Instead, the
corresponding SMC calls should be used to make the secure software
running in EL3 mode access it for us. Those SMC calls are handled by
LDFW (Loadable Firmware), which has to be loaded first. For example, for
E850-96 board it's done in its board_init(), so by the time RNG
capabilities are needed the LDFW should be already loaded and TRNG
should be functional.

[1] drivers/char/hw_random/exynos-trng.c
[2] dts/upstream/Bindings/rng/samsung,exynos5250-trng.yaml

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
rng: Introduce SPL_DM_RNG 2024-05-05T14:21:39+00:00 Marek Vasut marex@denx.de 2024-04-25T23:02:07+00:00 591257b05caba725eb57ceb174317ab4c7e460a7 Add SPL variant of DM_RNG so that the DM_RNG can be disabled in SPL if necessary. This may be necessary due to e.g. size constraints of the SPL. Signed-off-by: Marek Vasut <marex@denx.de> 
Add SPL variant of DM_RNG so that the DM_RNG can be disabled in SPL
if necessary. This may be necessary due to e.g. size constraints of
the SPL.

Signed-off-by: Marek Vasut <marex@denx.de>
rng: Add Turris Mox rTWM RNG driver 2024-03-05T07:27:59+00:00 Max Resch resch.max@gmail.com 2024-02-15T16:57:57+00:00 d61b485dbd766970816ae9da09004dc4b30f8395 A RNG driver for Armada 3720 boards running the Turris Mox rWTM firmware from CZ.NIC in the secure processor. Signed-off-by: Max Resch <resch.max@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> 
A RNG driver for Armada 3720 boards running the Turris Mox rWTM firmware
from CZ.NIC in the secure processor.

Signed-off-by: Max Resch <resch.max@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
rng: Add StarFive JH7110 RNG driver 2023-11-02T09:45:53+00:00 Chanho Park chanho61.park@samsung.com 2023-11-01T12:16:50+00:00 ebaee701a6a370b7566107d495db87ba653cc7c4 Adds to support JH7110 TRNG driver which is based on linux kernel's jh7110-trng.c. This can support to generate 256-bit random numbers and 128-bit but this makes 256-bit default for convenience. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
Adds to support JH7110 TRNG driver which is based on linux kernel's
jh7110-trng.c. This can support to generate 256-bit random numbers and
128-bit but this makes 256-bit default for convenience.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
rng: Provide a RNG based on the RISC-V Zkr ISA extension 2023-11-02T08:22:06+00:00 Heinrich Schuchardt heinrich.schuchardt@canonical.com 2023-10-31T12:55:52+00:00 ceec977ba1a994df423cd8558f72d6582e63da08 The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It provides an interface to a physical entropy source. A RNG driver based on the seed CSR is provided. It depends on mseccfg.sseed being set in the SBI firmware. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It
provides an interface to a physical entropy source.

A RNG driver based on the seed CSR is provided. It depends on
mseccfg.sseed being set in the SBI firmware.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
driver: rng: Add DM_RNG interface for ARMv8.5 RNDR registers 2023-10-11T17:22:32+00:00 Andre Przywara andre.przywara@arm.com 2023-08-30T11:32:30+00:00 31565bb0aa2d76b6941e96bcdbd204bae49ca828 The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS system registers, that provide 64 bits worth of randomness on every read. Since it's an extension, and implementing it is optional, there is a field in the ID_AA64ISAR0_EL1 ID register to query the availability of those registers. Add a UCLASS_RNG driver that returns entropy via repeated reads from those system registers, if the extension is implemented. The driver always binds, but checks the availability in the probe() routine. This helps systems which suffer from low boot entropy, since U-Boot can provide entropy via the generic UEFI entropy gathering protocol to the OS, at an early stage. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS
system registers, that provide 64 bits worth of randomness on every
read. Since it's an extension, and implementing it is optional, there is
a field in the ID_AA64ISAR0_EL1 ID register to query the availability
of those registers.

Add a UCLASS_RNG driver that returns entropy via repeated reads from
those system registers, if the extension is implemented.
The driver always binds, but checks the availability in the probe()
routine.

This helps systems which suffer from low boot entropy, since U-Boot can
provide entropy via the generic UEFI entropy gathering protocol to the OS,
at an early stage.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
rng: stm32: rename STM32 RNG driver 2023-10-04T11:26:02+00:00 Gatien Chevallier gatien.chevallier@foss.st.com 2023-09-19T15:27:53+00:00 77e0c6087923574579abe1a04538bb4982e33d55 Rename the RNG driver as it is usable by other STM32 platforms than the STM32MP1x ones. Rename CONFIG_RNG_STM32MP1 to CONFIG_RNG_STM32 Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Grzegorz Szymaszek <gszymaszek@short.pl> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> 
Rename the RNG driver as it is usable by other STM32 platforms
than the STM32MP1x ones. Rename CONFIG_RNG_STM32MP1 to
CONFIG_RNG_STM32

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
tpm: rng: Add driver model interface for TPM RNG device 2022-08-02T20:50:02+00:00 Sughosh Ganu sughosh.ganu@linaro.org 2022-07-22T16:02:04+00:00 e67ffb5aa5ab03a89305f4575ad3142486f9a306 The TPM device has a builtin random number generator(RNG) functionality. Expose the RNG functions of the TPM device to the driver model so that they can be used by the EFI_RNG_PROTOCOL if the protocol is installed. Also change the function arguments and return type of the random number functions to comply with the driver model api. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> 
The TPM device has a builtin random number generator(RNG)
functionality. Expose the RNG functions of the TPM device to the
driver model so that they can be used by the EFI_RNG_PROTOCOL if the
protocol is installed.

Also change the function arguments and return type of the random
number functions to comply with the driver model api.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
drivers: rng: add smccc trng driver 2022-06-23T17:12:56+00:00 Etienne Carriere etienne.carriere@linaro.org 2022-06-01T08:27:34+00:00 53355bb86c25d9cced1493df9fc95140acece556 Adds random number generator driver using Arm SMCCC TRNG interface to get entropy bytes from secure monitor. The driver registers as an Arm SMCCC feature driver to allow PSCI driver to bind a device for when secure monitor exposes RNG support from Arm SMCCC TRNG interface. Cc: Sughosh Ganu <sughosh.ganu@linaro.org> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> 
Adds random number generator driver using Arm SMCCC TRNG interface to
get entropy bytes from secure monitor. The driver registers as an
Arm SMCCC feature driver to allow PSCI driver to bind a device for
when secure monitor exposes RNG support from Arm SMCCC TRNG interface.

Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>