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<title>u-boot.git/drivers/rng, branch v2023.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/rng?h=v2023.01</id>
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<updated>2022-09-14T19:23:03Z</updated>
<entry>
<title>drivers: rng: optee_rng: register to CONFIG_OPTEE_SERVICE_DISCOVERY</title>
<updated>2022-09-14T19:23:03Z</updated>
<author>
<name>Etienne Carriere</name>
<email>etienne.carriere@linaro.org</email>
</author>
<published>2022-07-26T14:21:43Z</published>
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<id>urn:sha1:57fb86a97d75dbf9898bce50813cf63106da08ac</id>
<content type='text'>
Changes optee_rng driver to register itself has a OP-TEE service so
that a device is bound for the driver when OP-TEE enumerates the
PTA RNG service.

Cc: Sughosh Ganu &lt;sughosh.ganu@linaro.org&gt;
Cc: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Signed-off-by: Etienne Carriere &lt;etienne.carriere@linaro.org&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
</content>
</entry>
<entry>
<title>tpm: rng: Add driver model interface for TPM RNG device</title>
<updated>2022-08-02T20:50:02Z</updated>
<author>
<name>Sughosh Ganu</name>
<email>sughosh.ganu@linaro.org</email>
</author>
<published>2022-07-22T16:02:04Z</published>
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<id>urn:sha1:e67ffb5aa5ab03a89305f4575ad3142486f9a306</id>
<content type='text'>
The TPM device has a builtin random number generator(RNG)
functionality. Expose the RNG functions of the TPM device to the
driver model so that they can be used by the EFI_RNG_PROTOCOL if the
protocol is installed.

Also change the function arguments and return type of the random
number functions to comply with the driver model api.

Signed-off-by: Sughosh Ganu &lt;sughosh.ganu@linaro.org&gt;
Reviewed-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
Signed-off-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
</content>
</entry>
<entry>
<title>rng: stm32mp1_rng: add conditional reset feature for STM32MP13x</title>
<updated>2022-07-12T09:47:34Z</updated>
<author>
<name>Lionel Debieve</name>
<email>lionel.debieve@foss.st.com</email>
</author>
<published>2022-06-30T08:20:15Z</published>
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<id>urn:sha1:12e11aae2d96d4c437c4c068e440ab4b7f08ceb0</id>
<content type='text'>
New IP adds a conditional reset that impact the clock
error management. It is now linked to a new compatible.

Signed-off-by: Lionel Debieve &lt;lionel.debieve@foss.st.com&gt;
Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
<entry>
<title>drivers: rng: add smccc trng driver</title>
<updated>2022-06-23T17:12:56Z</updated>
<author>
<name>Etienne Carriere</name>
<email>etienne.carriere@linaro.org</email>
</author>
<published>2022-06-01T08:27:34Z</published>
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<id>urn:sha1:53355bb86c25d9cced1493df9fc95140acece556</id>
<content type='text'>
Adds random number generator driver using Arm SMCCC TRNG interface to
get entropy bytes from secure monitor. The driver registers as an
Arm SMCCC feature driver to allow PSCI driver to bind a device for
when secure monitor exposes RNG support from Arm SMCCC TRNG interface.

Cc: Sughosh Ganu &lt;sughosh.ganu@linaro.org&gt;
Cc: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Signed-off-by: Etienne Carriere &lt;etienne.carriere@linaro.org&gt;
</content>
</entry>
<entry>
<title>rng: nuvoton: Add NPCM7xx rng driver</title>
<updated>2022-06-10T17:37:32Z</updated>
<author>
<name>Jim Liu</name>
<email>jim.t90615@gmail.com</email>
</author>
<published>2022-05-24T08:56:57Z</published>
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<id>urn:sha1:866eab1d28b5cee39da50c9392bb5112b4865656</id>
<content type='text'>
Add Nuvoton BMC NPCM750 rng driver.

Signed-off-by: Jim Liu &lt;JJLIU0@nuvoton.com&gt;
</content>
</entry>
<entry>
<title>rng: add OP-TEE based Random Number Generator</title>
<updated>2022-04-11T14:28:04Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@foss.st.com</email>
</author>
<published>2022-03-29T12:21:23Z</published>
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<id>urn:sha1:fd52e7f9c775b71f64c4348703a7cc60f5fc8cf8</id>
<content type='text'>
Add driver for OP-TEE based Random Number Generator on ARM SoCs
where hardware entropy sources are not accessible to normal world
and the RNG service is provided by a HWRNG Trusted Application (TA).

This driver is based on the linux driver: char/hw_random/optee-rng.c

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
</content>
</entry>
<entry>
<title>clk: Add clk_get_by_name_optional</title>
<updated>2022-02-25T06:41:04Z</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2022-01-15T20:52:47Z</published>
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<id>urn:sha1:e96e2132f977aab738994c11162b14695029be6e</id>
<content type='text'>
This adds a helper function for clk_get_by_name in cases where the clock is
optional. Hopefully this helps point driver writers in the right direction.
Also convert some existing users.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Link: https://lore.kernel.org/r/20220115205247.566210-2-seanga2@gmail.com
</content>
</entry>
<entry>
<title>Kconfig: Remove all default n/no options</title>
<updated>2021-08-31T21:47:49Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2021-08-27T06:48:10Z</published>
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<id>urn:sha1:b4c2c151b14b59a2403675526adf666710cade67</id>
<content type='text'>
default n/no doesn't need to be specified. It is default option anyway.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
[trini: Rework FSP_USE_UPD portion]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>dm: define LOG_CATEGORY for all uclass</title>
<updated>2021-07-06T16:38:03Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@foss.st.com</email>
</author>
<published>2021-04-27T09:02:19Z</published>
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<id>urn:sha1:b953ec2bca1ebe059366e870eb4bec5e7af9c36b</id>
<content type='text'>
Define LOG_CATEGORY for all uclass to allow filtering with
log command.

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rng: iproc_rng200: Enable support for RPi4 armv7</title>
<updated>2021-03-02T12:53:48Z</updated>
<author>
<name>Matthias Brugger</name>
<email>mbrugger@suse.com</email>
</author>
<published>2021-02-26T10:48:00Z</published>
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<id>urn:sha1:3ac05239b48c8acae370cd0f68ec5cb0150bc95c</id>
<content type='text'>
On the RPi4 armv7 build we have the situationt that we use physical
addresses of 64 bit, while the virtual addresses are 32 bit.
Remap the base address in this scenario via map_physmem().

Signed-off-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
</content>
</entry>
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