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<title>u-boot.git/drivers/rng, branch v2024.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/rng?h=v2024.01</id>
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<updated>2023-11-02T09:45:53Z</updated>
<entry>
<title>rng: Add StarFive JH7110 RNG driver</title>
<updated>2023-11-02T09:45:53Z</updated>
<author>
<name>Chanho Park</name>
<email>chanho61.park@samsung.com</email>
</author>
<published>2023-11-01T12:16:50Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ebaee701a6a370b7566107d495db87ba653cc7c4'/>
<id>urn:sha1:ebaee701a6a370b7566107d495db87ba653cc7c4</id>
<content type='text'>
Adds to support JH7110 TRNG driver which is based on linux kernel's
jh7110-trng.c. This can support to generate 256-bit random numbers and
128-bit but this makes 256-bit default for convenience.

Signed-off-by: Chanho Park &lt;chanho61.park@samsung.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>rng: Provide a RNG based on the RISC-V Zkr ISA extension</title>
<updated>2023-11-02T08:22:06Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2023-10-31T12:55:52Z</published>
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<id>urn:sha1:ceec977ba1a994df423cd8558f72d6582e63da08</id>
<content type='text'>
The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It
provides an interface to a physical entropy source.

A RNG driver based on the seed CSR is provided. It depends on
mseccfg.sseed being set in the SBI firmware.

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>drivers: rng: add support for Meson S4</title>
<updated>2023-10-13T09:30:42Z</updated>
<author>
<name>Alexey Romanov</name>
<email>avromanov@salutedevices.com</email>
</author>
<published>2023-10-12T07:58:25Z</published>
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<id>urn:sha1:a92345610ed3596bc25de08b17cb29c86b508e6c</id>
<content type='text'>
For some Amlogic SOC's, mechanism to obtain random number
has been changed. For example, S4 now uses status bit waiting algo.

Signed-off-by: Alexey Romanov &lt;avromanov@salutedevices.com&gt;
Reviewed-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Link: https://lore.kernel.org/r/20231012075828.22685-2-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
</content>
</entry>
<entry>
<title>driver: rng: Add DM_RNG interface for ARMv8.5 RNDR registers</title>
<updated>2023-10-11T17:22:32Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2023-08-30T11:32:30Z</published>
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<id>urn:sha1:31565bb0aa2d76b6941e96bcdbd204bae49ca828</id>
<content type='text'>
The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS
system registers, that provide 64 bits worth of randomness on every
read. Since it's an extension, and implementing it is optional, there is
a field in the ID_AA64ISAR0_EL1 ID register to query the availability
of those registers.

Add a UCLASS_RNG driver that returns entropy via repeated reads from
those system registers, if the extension is implemented.
The driver always binds, but checks the availability in the probe()
routine.

This helps systems which suffer from low boot entropy, since U-Boot can
provide entropy via the generic UEFI entropy gathering protocol to the OS,
at an early stage.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rng: stm32: Implement custom RNG configuration support</title>
<updated>2023-10-04T11:26:03Z</updated>
<author>
<name>Gatien Chevallier</name>
<email>gatien.chevallier@foss.st.com</email>
</author>
<published>2023-09-19T15:27:58Z</published>
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<id>urn:sha1:e077d7f61309d83fa94c55b17bfccc255b4467fb</id>
<content type='text'>
STM32 RNG configuration should best fit the requirements of the
platform. Therefore, put a platform-specific RNG configuration
field in the platform data. Default RNG configuration for STM32MP13
is the NIST certified configuration [1].

While there, fix and the RNG init sequence to support all RNG
versions.

[1] https://csrc.nist.gov/projects/cryptographic-module-validation-program/entropy-validations/certificate/53

Signed-off-by: Gatien Chevallier &lt;gatien.chevallier@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
<entry>
<title>rng: stm32: add error concealment sequence</title>
<updated>2023-10-04T11:26:03Z</updated>
<author>
<name>Gatien Chevallier</name>
<email>gatien.chevallier@foss.st.com</email>
</author>
<published>2023-09-19T15:27:57Z</published>
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<id>urn:sha1:6032292534e0f47012edd76cd88b2c952856f928</id>
<content type='text'>
Seed errors can occur when using the hardware RNG. Implement the
sequences to handle them. This avoids irrecoverable RNG state.

Try to conceal seed errors when possible. If, despite the error
concealing tries, a seed error is still present, then return an error.

A clock error does not compromise the hardware block and data can
still be read from RNG_DR. Just warn that the RNG clock is too slow
and clear RNG_SR.

Signed-off-by: Gatien Chevallier &lt;gatien.chevallier@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
<entry>
<title>rng: stm32: add RNG clock frequency restraint</title>
<updated>2023-10-04T11:26:03Z</updated>
<author>
<name>Gatien Chevallier</name>
<email>gatien.chevallier@foss.st.com</email>
</author>
<published>2023-09-19T15:27:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=01af3636230656cdcba7a1c625c17a5c32a3fb69'/>
<id>urn:sha1:01af3636230656cdcba7a1c625c17a5c32a3fb69</id>
<content type='text'>
In order to ensure a good RNG quality and compatibility with
certified RNG configuration, add RNG clock frequency restraint.

Signed-off-by: Gatien Chevallier &lt;gatien.chevallier@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
<entry>
<title>rng: stm32: Implement configurable RNG clock error detection</title>
<updated>2023-10-04T11:26:03Z</updated>
<author>
<name>Gatien Chevallier</name>
<email>gatien.chevallier@foss.st.com</email>
</author>
<published>2023-09-19T15:27:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2d2574b4055f86f2fac57c6322e6487f15524baf'/>
<id>urn:sha1:2d2574b4055f86f2fac57c6322e6487f15524baf</id>
<content type='text'>
RNG clock error detection is now enabled if the "clock-error-detect"
property is set in the device tree.

Signed-off-by: Gatien Chevallier &lt;gatien.chevallier@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
<entry>
<title>rng: stm32: rename STM32 RNG driver</title>
<updated>2023-10-04T11:26:02Z</updated>
<author>
<name>Gatien Chevallier</name>
<email>gatien.chevallier@foss.st.com</email>
</author>
<published>2023-09-19T15:27:53Z</published>
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<id>urn:sha1:77e0c6087923574579abe1a04538bb4982e33d55</id>
<content type='text'>
Rename the RNG driver as it is usable by other STM32 platforms
than the STM32MP1x ones. Rename CONFIG_RNG_STM32MP1 to
CONFIG_RNG_STM32

Signed-off-by: Gatien Chevallier &lt;gatien.chevallier@foss.st.com&gt;
Reviewed-by: Grzegorz Szymaszek &lt;gszymaszek@short.pl&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
<entry>
<title>rockchip: rng: add trngv1 for rk3588</title>
<updated>2023-04-21T07:16:01Z</updated>
<author>
<name>Chris Morgan</name>
<email>macromorgan@hotmail.com</email>
</author>
<published>2023-04-13T14:13:02Z</published>
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<id>urn:sha1:5891282bf399b073eb747269117732a7de2845ed</id>
<content type='text'>
This adds support for the TRNG found in the RK3588 SoC to the
rockchip_rng driver so that it can be used for things such as
seeding randomness to Linux.

Changes in V3:
 - Moved notes from commit to cover letter.
 - Added Reviewed-By tag.

Changes in V2:
 - Modified Kconfig to note that the Rockchip RNG driver supports all
   versions of the hardware (v1, v2, and the trng in the rk3588).

Signed-off-by: Lin Jinhan &lt;troy.lin@rock-chips.com&gt;
Signed-off-by: Chris Morgan &lt;macromorgan@hotmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
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