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<title>u-boot.git/drivers/serial/Kconfig, branch v2024.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/serial/Kconfig?h=v2024.01</id>
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<updated>2023-11-07T12:47:08Z</updated>
<entry>
<title>serial: zynqmp: Fetch baudrate from dtb and update</title>
<updated>2023-11-07T12:47:08Z</updated>
<author>
<name>Algapally Santosh Sagar</name>
<email>santoshsagar.algapally@amd.com</email>
</author>
<published>2023-09-21T11:20:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bd9ff681bdd1893d11ab8d4ea79a9f74d0fffdb7'/>
<id>urn:sha1:bd9ff681bdd1893d11ab8d4ea79a9f74d0fffdb7</id>
<content type='text'>
The baudrate configured in .config is taken by default by serial. If
change of baudrate is required then the .config needs to changed and
u-boot recompilation is required or the u-boot environment needs to be
updated.

To avoid this, support is added to fetch the baudrate directly from the
device tree file and update.
The serial, prints the log with the configured baudrate in the dtb.
The commit c4df0f6f315c ("arm: mvebu: Espressobin: Set default value for
$fdtfile env variable") is taken as reference for changing the default
environment variable.

The default environment stores the default baudrate value, When default
baudrate and dtb baudrate are not same glitches are seen on the serial.
So, the environment also needs to be updated with the dtb baudrate to
avoid the glitches on the serial.

Also add test to cover this new function.

Signed-off-by: Algapally Santosh Sagar &lt;santoshsagar.algapally@amd.com&gt;
Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
Link: https://lore.kernel.org/r/20230921112043.3144726-3-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>configs: Add support in Kconfig and convert for armada boards</title>
<updated>2023-11-07T12:47:08Z</updated>
<author>
<name>Algapally Santosh Sagar</name>
<email>santoshsagar.algapally@amd.com</email>
</author>
<published>2023-09-21T11:20:42Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8819892bdbcfe8797bb1ebf45806d9b5ebb86674'/>
<id>urn:sha1:8819892bdbcfe8797bb1ebf45806d9b5ebb86674</id>
<content type='text'>
Move the DEFAULT_ENV_IS_RW to Kconfig for easier configuration.
Hence, add the CONFIG_DEFAULT_ENV_IS_RW config to the defconfig files
to allow enabling them for armada boards.

Signed-off-by: Algapally Santosh Sagar &lt;santoshsagar.algapally@amd.com&gt;
Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Link: https://lore.kernel.org/r/20230921112043.3144726-2-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>serial: Drop mention of SPL/TPL_SYS_MALLOC_F</title>
<updated>2023-10-06T18:38:12Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-09-26T14:14:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=77b9b187e99776996ff67b7dbdcb313d3790fa7b'/>
<id>urn:sha1:77b9b187e99776996ff67b7dbdcb313d3790fa7b</id>
<content type='text'>
These symbols do not (yet) exist, so drop the usage of them in the
serial Kconfig file. It has no effect.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spl: Use CONFIG_SPL... instead of CONFIG_..._SPL_...</title>
<updated>2023-10-06T18:38:11Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-09-26T14:14:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=82e26e0d6883673bdedbcdb0ddd4bc967ce6ce70'/>
<id>urn:sha1:82e26e0d6883673bdedbcdb0ddd4bc967ce6ce70</id>
<content type='text'>
We like to put the SPL first so it is clear that it relates to SPL. Rename
various malloc-related options which have crept in, to stick to this
convention.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Marcel Ziswiler &lt;marcel.ziswiler@toradex.com&gt;
Reviewed-by: Martyn Welch &lt;martyn.welch@collabora.com&gt;
Reviewed-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'next'</title>
<updated>2023-10-02T14:55:44Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-10-02T14:55:44Z</published>
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<id>urn:sha1:ac897385bbfa30cfdfb62ccf24acfcd4b274b2ff</id>
<content type='text'>
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Look for DBG2 UART in SPL too</title>
<updated>2023-09-21T22:03:46Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-09-20T03:00:07Z</published>
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<id>urn:sha1:b1350636e69d4aac1e00aee5a327b5724f074420</id>
<content type='text'>
If coreboot does not set up sysinfo for the UART, SPL currently hangs.
Use the DBG2 technique there as well. This allows coreboot64 to boot from
coreboot even if the console info is missing from sysinfo

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>risc-v: implement DBCN based debug console</title>
<updated>2023-09-05T02:53:55Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2023-09-04T11:24:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dfe08374943c0e898fcfaf7327f69e0fb56b7d23'/>
<id>urn:sha1:dfe08374943c0e898fcfaf7327f69e0fb56b7d23</id>
<content type='text'>
Use the DBCN SBI extension to implement a debug console.
Make it the default for S-mode RISC-V.

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>Kconfigs: Correct default of "0" on hex type entries</title>
<updated>2023-08-09T13:21:42Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-08-02T15:09:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a077ac13d03c8cde646ddab30b03ec0f8b753e1e'/>
<id>urn:sha1:a077ac13d03c8cde646ddab30b03ec0f8b753e1e</id>
<content type='text'>
It is not a parse error to have a default value of "0" for a "hex" type
entry, instead of "0x0".  However, "0" and "0x0" are not treated the
same even by the tools themselves. Correct this by changing the default
value from "0" to "0x0" for all hex type questions that had the
incorrect default. Fix one instance (in two configs) of a default of "0"
being used on a hex question to be "0x0". Remove the cases where a
defconfig had set a value of "0x0" to be used as the default had been
"0".

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>serial: mxs: Add MXS AUART driver</title>
<updated>2023-05-21T14:54:41Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2023-05-06T14:43:31Z</published>
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<id>urn:sha1:ff476897ed698eae1fa439d52b30694a2b40464a</id>
<content type='text'>
Add trivial driver for the MXS AUART IP. This is the other UART IP
present in i.MX23 and i.MX28, used to drive the non-DUART ports.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>x86: Allow locating the UART from ACPI tables</title>
<updated>2023-05-11T02:25:29Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-05-04T22:55:00Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b29dbf98baa35441ad01957bb2317cb4f70f390f'/>
<id>urn:sha1:b29dbf98baa35441ad01957bb2317cb4f70f390f</id>
<content type='text'>
When coreboot does not pass a UART in its sysinfo struct, there is no
easy way to find it out.

Since coreboot does not actually init the serial device when serial is
disabled, it is not possible to make it add this information to the
sysinfo table.

Add a way to obtain this information from the DBG2 ACPI table, which is
normally set up by coreboot.

For now this only supports a memory-mapped 16550-style UART.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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