u-boot.git/drivers/serial/serial_lpuart.c, branch main

serial: lpuart: Clear the OR STAT in tstc to prevent hang

2026-07-12T08:18:32Z

Clear the STAT register OR bit every time in .tstc callback, otherwise a condition may occur when data are fed into the RX FIFO, the FIFO did overflow, the OR bit is set and prevents any new data from being added into the RX FIFO, the OR bit is never cleared, and watermark read back is always 0. If this condition occurs, the .tstc callback will always report no new characters, and the OR bit will never be cleared, so the U-Boot shell will be unresponsive until next reboot or kernel boot. This is easy to trigger on MX95, power on the system and send traffic on UART from host to the MX95, the MX95 FIFO will overflow and the U-Boot console will become unresponsive. Fix this by clearing the OR bit early, in .tstc callback. This way, even if an overflow occurs, there will be slight loss of RX data, but the U-Boot console will not become unresponsive. Signed-off-by: Marek Vasut Signed-off-by: Peng Fan

serial: lpuart: Use livetree API for fdt access

2026-06-26T20:06:39Z

Use livetree API, otherwise driver will fail to read properties from the device tree when OF_LIVE is enabled. Signed-off-by: Peng Fan

serial: lpuart: Fix RX FIFO Enable bitmask

2026-06-10T20:49:55Z

The Receive FIFO Enable (RXFE) field in the LPUART FIFO register is bit 3 on all supported architectures. The define has been wrong since it was introduced: for non-i.MX8/i.MXRT it set bit 6, which on LS102xA is read-only-as-zero, so the bug went unnoticed. NXP confirmed bit 3 is correct everywhere, so drop the ARCH-based selection. Link: https://github.com/nxp-imx/uboot-imx/commit/9498bcc514737269bb0ca436f775460741ab8199 Link: https://lore.kernel.org/u-boot/dc163ea7-9063-4dfb-a39a-e643c0bcccf1@oss.nxp.com/ Fixes: 6209e14cb026 ("serial: lpuart: add 32-bit registers lpuart support") Signed-off-by: Emanuele Ghidoli Reviewed-by: Francesco Dolcini Reviewed-by: Sébastien Szymanski

serial: lpuart: Return value from correct variable

2025-08-27T07:52:20Z

In get_lpuart_clk_rate if the call to clk_get_rate returns an error then the call to return should pass the value of the error which is in rate rather than ret which will be 0 as its value is not affected by this error. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Peng Fan

drivers: serial: Remove duplicate newlines

2024-07-22T16:53:06Z

Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut

Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"

2024-05-20T19:35:03Z

As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

2024-05-19T14:16:36Z

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

serial: Remove and add needed includes

2024-05-07T14:00:56Z

Remove from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson Signed-off-by: Tom Rini

serial: lpuart: use ipg clk for i.MX7ULP

2024-04-15T11:09:31Z

To i.MX7ULP compatible lpuart, there is only ipg clk, no per clk. So add a devtype check for i.MX7ULP. Signed-off-by: Peng Fan

serial: lpuart: Enable IPG clock

2023-10-16T12:02:38Z

Current codes only ennable the PER clock. However on iMX8 the LPUART also needs IPG clock which is an LPCG. Should not depend on the default LPCG setting. Signed-off-by: Ye Li Reviewed-by: Peng Fan Signed-off-by: Sébastien Szymanski