u-boot.git/drivers/serial, branch next

Merge tag 'mediatek-for-next-2026-08-24' of https://git.u-boot-project.org/u-boot/custodians/u-boot-mediatek into next

2026-08-25T17:36:46Z

* New HDMI PHY and I2C DDC drivers, default EDID_ADDR macro * MT8189 clock qualifier fix * Phase-aware PSCI reset (MT8195/MT8365) * dwc_eth_qos MT8366 support * MediaTek TPHY v3 hardware support * mtk_snor mt8188/mt8189 compatible-string cleanup * MT6358/MT6366 PMIC regulator + pwrap support * MediaTek pinctrl Kconfig cleanup (per-SoC symbols → single driver + TARGET_*) * New MT8366 pinctrl driver + dt-bindings header * MediaTek serial driver clock-handling fixes

serial: mtk: drop check before clk_bus enable

2026-08-25T00:56:02Z

Drop the redundant check that clk_bus.dev is valid before enabling it. clk_enable() already calls clk_valid() which does the same check. Link: https://patch.msgid.link/20260807-serial-mtk-clock-fixes-v3-4-8cc94d313b57@baylibre.com Signed-off-by: David Lechner

serial: mtk: return error value from clk_get_rate()

2026-08-25T00:55:51Z

Pass the return value from clk_get_rate() instead of changing it to -EINVAL. These return values are either ignored or logged, so it should make debugging easier in the cases where it is logged. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260807-serial-mtk-clock-fixes-v3-3-8cc94d313b57@baylibre.com Signed-off-by: David Lechner

serial: mtk: guard clk_get_rate() with clk_valid()

2026-08-25T00:55:35Z

Check that priv->clk has been populated before trying to use it in the MediaTek serial driver. The clock is optional and may not be populated in all cases (in which case it is expected that there was a fixed clock rate provided.) Note this changes behavior slightly: previously, a populated clock whose clk_get_rate() failed silently fell back to priv->fixed_clk_rate (which is only set from DT when clk_get_by_index() failed, so it would have been 0 here). Now an error is returned instead. Fixes: 3b17f2e2c2a9 ("serial: mtk: add support for using dynamic baud clock souce") Signed-off-by: Suhrid Subramaniam Link: https://patch.msgid.link/20260807-serial-mtk-clock-fixes-v3-2-8cc94d313b57@baylibre.com Signed-off-by: David Lechner

serial: mtk: use ulong for clk_rate

2026-08-25T00:50:22Z

Use ulong for return value of clk_get_rate() in the MediaTek serial driver. IS_ERR_VALUE() does a signed 64-bit comparison against the range of possible error codes. If clk_get_rate() returns an error, assigning this to a u32 truncates the top 32 bits making the value smaller, defeating IS_ERR_VALUE() and producing a garbage divisor that hangs the UART. Fixes: 3b17f2e2c2a9 ("serial: mtk: add support for using dynamic baud clock souce") Signed-off-by: Suhrid Subramaniam Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260807-serial-mtk-clock-fixes-v3-1-8cc94d313b57@baylibre.com Signed-off-by: David Lechner

serial: lpuart: test the receive flag, not the FIFO counter

2026-08-14T19:14:01Z

On the 8 bit register variant, the only user of which is fsl,vf610-lpuart, _lpuart_serial_init() disables the FIFO: /* Disable FIFO and flush buffer */ __raw_writeb(0x0, &base->upfifo); while _lpuart_serial_tstc() asks the receive FIFO counter whether a character arrived: if (__raw_readb(&base->urcfifo) == 0) return 0; With the FIFO disabled the dataword lands in the data register and raises S1[RDRF], but RCFIFO stays zero, so tstc() never reports a character. The console is then output only: autoboot cannot be interrupted, ctrlc() never fires, and anything polling for a key waits forever. _lpuart_serial_getc() in the same driver already tests S1, and the 32 bit variant enables its FIFO in _lpuart32_serial_init() before reading the RXCOUNT field of WATER, so only this path is inconsistent. Test S1 the way getc() does. Tested on a Colibri VF50: U-Boot printed its whole log over UART0 but accepted no input at all, neither a key during the boot delay nor Ctrl-C during a sleep, while Linux received on the same pads with the same pin mux. With the fix the boot delay can be interrupted, including with bootdelay=0, where the key is already buffered when abortboot_single_key() checks. Signed-off-by: Mehmet Fide

serial: coreboot: Accept DBG2 subtype 0x12

2026-08-10T20:22:09Z

U-Boot running as a coreboot payload obtains serial console information either from the coreboot table or from the ACPI DBG2 table. When serial console support is disabled in coreboot, the coreboot table does not contain serial information. In this case U-Boot falls back to parsing the DBG2 table. Some AMD platforms or any other platforms that uses memory-mapped I/O advertise the debug UART using DBG2 subtype 0x0012 ("16550-compatible with parameters defined in Generic Address Structure"). U-Boot currently accepts only subtype 0x0000, causing DBG2 UART detection to fail and leaving no console output. Accept subtype 0x0012 as well and keep the existing handling logic. Signed-off-by: Desapogu Jayaramudu Reviewed-by: Simon Glass

serial: avoid redundant early UART initialization

2026-07-28T18:30:55Z

When DEBUG_UART and SKIP_EARLY_DM are enabled, the serial console is still probed before relocation even though DEBUG_UART already configures the UART and provides early console output. The debug UART configuration is sufficient until relocation, making full serial driver initialization at this stage unnecessary. Furthermore, the initialization is slow since it runs with dcache disabled and is repeated again after relocation. Skip pre-relocation serial probing in this configuration and defer full UART initialization until after relocation. Update the GENI UART probe logic accordingly. This removes redundant UART initialization and improves boot performance. Signed-off-by: Aswin Murugan

serial: sifive: remove busy-loops from getc and putc ops

2026-07-27T04:04:42Z

The DM serial framework in __serial_getc() and __serial_putc() already retries when driver ops return -EAGAIN, calling schedule() between attempts to service the watchdog. sifive_serial_getc() and sifive_serial_putc() spin internally on -EAGAIN, which prevents the framework from calling schedule(). This can lead to watchdog timeouts when waiting for RX data or TX FIFO space. Remove the busy-loops and return -EAGAIN directly from the underlying helpers, letting the framework handle retries with proper watchdog servicing. This is consistent with how other DM serial drivers (pl01x, meson, cortina, etc.) implement their ops. Signed-off-by: Naveen Kumar Chaudhary Reviewed-by: Leo Yu-Chi Liang

serial: esp32: add driver for esp32 series chips

2026-07-23T21:16:22Z

Add a driver model serial driver for Espressif ESP32 UART controllers. The driver supports ESP32, ESP32-S3 and ESP32-S31 UART register variants, including baud-rate setup, FIFO access and basic port initialization. Signed-off-by: Honbo He Changes in v3: - Add debug UART for early print output