Now when all infrastructure in ARC is ready for it let's switch ARC UART
to driver model.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>

Being global variable with 0 value it falls into .bss area which we may
only use after relocation to RAM. And right afetr relocation we zero
.bss - effectively cleaing register address set for early console.

Now with pre-set value "regs" variable is no longer in .bss and this way
safely survives relocation.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Serial-uclass should be generically implemented without depending
a particular hardware.  Fortunately, nothing in include/ns16550.h is
referenced from drivers/serial/serial-uclass.c, so remove this bogus
include.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>

Panasonic's System LSI products, UniPhier SoC family, have been
transferred to Socionext Inc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Fix trivial typo.

Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Axel Lin <axel.lin@ingics.com>

We do not have to set the LCR register every time we change the
baud-rate.  We just need to set it up once in the probe function.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

For PH1-Pro4, the 8 bit write access to LCR register (offset = 0x11)
is not working correctly.  As a side effect, it also modifies MCR
register (offset = 0x10) and results in unexpected behavior.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

The formula to calculate SCIF BRR for R-Car H2/M2/E2 SoCs is as follows:

BRR = pclk / (64 * 2^(2n-1) * baudrate) - 1,
the prescaler is 0 due to SCSMR settings, hence n=0

Also SCSCR must be set to use internal or external clock source.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>