u-boot.git/drivers/serial, branch v2020.04-rc4 Unnamed repository; edit this file 'description' to name the repository. serial: mcfuart: renaming to a more appropriate name 2020-03-13T13:29:50+00:00 Angelo Durgehello angelo.dureghello@timesys.com 2020-02-29T00:09:35+00:00 1886024a0e17a37d86dce622e395e37262d7bc3a All drivers seems to align now to serial_xxx maning, so, aligning also this driver, to allow to be found easily. Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com> 
All drivers seems to align now to serial_xxx maning, so, aligning
also this driver, to allow to be found easily.

Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
serial: mcfuart: fix uart port index 2020-03-13T13:28:17+00:00 Angelo Durgehello angelo.dureghello@timesys.com 2020-02-29T00:01:32+00:00 ce5e3ea7995269a49a530284af25cc8cc44bb37d Actually, using dev->seq value before probe to deduce the current serial port index leads to reading an invalid seq value (-1). So, getting dev->seq at probe time. Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com> 
Actually, using dev->seq value before probe to deduce the current
serial port index leads to reading an invalid seq value (-1).
So, getting dev->seq at probe time.

Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
serial_lpuart: make clock failure less verbose 2020-03-09T14:06:23+00:00 Giulio Benetti giulio.benetti@benettiengineering.com 2020-01-31T13:39:47+00:00 289dd9f0720dbbefd6092b9388ad60cc42cb358a Some device may enable CONFIG_CLK but not still support this clock in CC, so better use debug() in place of dev_warn() otherwise a lot of boards will throw useless dev_warn()s. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
Some device may enable CONFIG_CLK but not still support this clock in
CC, so better use debug() in place of dev_warn() otherwise a lot of
boards will throw useless dev_warn()s.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
serial: ns16550: Move PCI access from ofdata_to_platdata() to probe() 2020-03-05T10:25:10+00:00 Wolfgang Wallner wolfgang.wallner@br-automation.com 2020-03-02T13:41:14+00:00 720f9e1fdb0c92d3fd16e1bfc25bcbd35612675c Currently the ofdata_to_platdata() method calls dev_read_addr_pci(), which potentially accesses the parent PCI bus. If this happens before the parent PCI bus is probed the resulting address will be wrong. This behavior was triggered by commit 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent"). According to a comment in drivers/pci/pci-uclass.c [1] accessing the PCI parent bus in ofdata_to_platdata() is not allowed, and the access should be moved to the probe() function. Move the call to dev_read_addr_pci() and the related handling of the 'addr' value from the ofdata_to_platdata() to its own function, which is then called from the probe() method. While moving the code, the comment /* try Processor Local Bus device first */ was dropped. It was initially added with commit 3db886a5bf38 ("serial: ns16550: Support ns16550 compatible pci uart devices") and later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function to read a PCI BAR"). [1] Comment in drivers/pci/pci-uclass.c: "A common cause of this problem is that this function is called in the ofdata_to_platdata() method of @dev. Accessing the PCI bus in that method is not allowed, since it has not yet been probed. To fix this, move that access to the probe() method of @dev instead." Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo 
Currently the ofdata_to_platdata() method calls dev_read_addr_pci(),
which potentially accesses the parent PCI bus. If this happens before
the parent PCI bus is probed the resulting address will be wrong.

This behavior was triggered by commit 82de42fa1468 ("dm: core:
Allocate parent data separate from probing parent").

According to a comment in drivers/pci/pci-uclass.c [1] accessing
the PCI parent bus in ofdata_to_platdata() is not allowed, and the
access should be moved to the probe() function.

Move the call to dev_read_addr_pci() and the related handling of the
'addr' value from the ofdata_to_platdata() to its own function,
which is then called from the probe() method.

While moving the code, the comment /* try Processor Local Bus device
first */ was dropped. It was initially added with commit 3db886a5bf38
("serial: ns16550: Support ns16550 compatible pci uart devices") and
later made obsolete with commit 33c215af4b9d ("dm: pci: Add a function
to read a PCI BAR").

[1] Comment in drivers/pci/pci-uclass.c:
"A common cause of this problem is that this function is called in the
ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
method is not allowed, since it has not yet been probed. To fix this,
move that access to the probe() method of @dev instead."

Fixes: 82de42fa1468 ("dm: core: Allocate parent data separate from probing parent")
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm 2020-02-11T15:58:41+00:00 Tom Rini trini@konsulko.com 2020-02-11T15:58:41+00:00 9a8942b53d57149754e0dfc975e0d92d1afd4087 sandbox conversion to SDL2 TPM TEE driver Various minor sandbox video enhancements New driver model core utility functions 
sandbox conversion to SDL2
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
serial: serial_cortina: add UART DM driver for CAxxxx SoCs 2020-02-07T21:16:01+00:00 Jason Li jason.li@cortina-access.com 2020-01-30T20:34:58+00:00 0de653d8cfa6eba4a9ffd1fc958a31b2d8818dff Add serial UART driver support for all Cortina Access CAxxxx family of SoCs. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Jason Li <jason.li@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> 
Add serial UART driver support for all Cortina Access
CAxxxx family of SoCs.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Jason Li <jason.li@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
dm: core: Create a new header file for 'compat' features 2020-02-06T02:33:46+00:00 Simon Glass sjg@chromium.org 2020-02-03T14:36:16+00:00 336d4615f8fa774557d14f9b3245daa9e5fe3dbc At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> 
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
dm: core: Require users of devres to include the header 2020-02-06T02:33:46+00:00 Simon Glass sjg@chromium.org 2020-02-03T14:36:15+00:00 61b29b82683863a970fd4609a7c58512872616bc At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> 
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
x86: serial: Add a coreboot serial driver 2020-02-03T17:19:25+00:00 Simon Glass sjg@chromium.org 2019-12-20T00:58:20+00:00 44482e8a2a33835563c17d49dac4004d4da0a7ea Coreboot can provide information about the serial device in use on a platform. Add a driver that uses this information to produce a working UART. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Coreboot can provide information about the serial device in use on a
platform. Add a driver that uses this information to produce a working
UART.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
serial: ns16550: Support run-time configuration 2020-02-03T17:19:13+00:00 Simon Glass sjg@chromium.org 2019-12-20T00:58:18+00:00 62cbde4c4e462e5147d07cf1424492bb39e7bf94 At present this driver uses an assortment of CONFIG options to control how it accesses the hardware. This is painful for platforms that are supposed to be controlled by a device tree or a previous-stage bootloader. Add a new CONFIG option to enable fully dynamic configuration. This controls register spacing, size, offset and endianness. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> 
At present this driver uses an assortment of CONFIG options to control
how it accesses the hardware. This is painful for platforms that are
supposed to be controlled by a device tree or a previous-stage bootloader.

Add a new CONFIG option to enable fully dynamic configuration. This
controls register spacing, size, offset and endianness.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Tested-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>